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A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2. [ABSTRACT FROM AUTHOR]

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm2 from a 1-V supply. The 2.25- $\mu \text{A}$ hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- $\mu \text{W}$ XO features a low-frequency inaccuracy of 4 ppm/V. The 40- $\mu \text{A}$ relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation. [ABSTRACT FROM AUTHOR]

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms. [ABSTRACT FROM AUTHOR]