Search

Blockchain consensus mechanisms play a critical role in ensuring the security, decentralization, and integrity of distributed networks. As blockchain technology expands beyond cryptocurrencies into broader applications such as supply chain management and healthcare, the importance of efficient and scalable consensus algorithms has grown significantly. This study provides a comprehensive bibliometric analysis of blockchain and consensus mechanism research from 2014 to 2024, using tools such as VOSviewer and R's Bibliometrix package. The analysis traces the evolution from foundational mechanisms like Proof of ork (PoW) to more advanced models such as Proof of Stake (PoS) and Byzantine Fault Tolerance (BFT), with particular emphasis on Ethereum's "The Merge" in 2022, which marked the historic shift from PoW to PoS. Key findings highlight emerging themes, including scalability, security, and the integration of blockchain with state-of-the-art technologies like artificial intelligence (AI), the Internet of Things (IoT), and energy trading. The study also identifies influential authors, institutions, and countries, emphasizing the collaborative and interdisciplinary nature of blockchain research. Through thematic analysis, this review uncovers the challenges and opportunities in decentralized systems, underscoring the need for continued innovation in consensus mechanisms to address efficiency, sustainability, scalability, and privacy concerns. These insights offer a valuable foundation for future research aimed at advancing blockchain technology across various industries. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is a non-volatile memory device with favorable characteristics such as persistence, byte-addressability, and lower latency when compared to flash memory. However, it comprises memory cells that have limited lifetime and higher access latency than DRAM. The row buffer size of a PCM is preferred to be larger than 128B to fill the latency gap between two memories and to reduce the metadata overhead incurred by wear leveling. As the cache line size in a general-purpose processor is 64B, a read-modify-write (RMW) module is required to be placed between the processor and the PCM, which in turn induces a performance degradation. To reduce such an overhead and enhance the reliability of a device, this paper presents a new RMW architecture. The proposed model introduces a DRAM cache in the RMW module, which minimizes redundant read operations for write operations by pre-fetching the entire transaction unit instead of merely caching the 64B requested data. Furthermore, a typeless merge operation is performed with the proposed cache by gathering multiple commands accessing consecutive addresses, irrespective of whether they are READ or WRITE. Simulation results indicate that the proposed method enhances the speed by 3.2 times and the reliability by 49 percent as compared to the baseline model. [ABSTRACT FROM AUTHOR]

A set-associative cache organization is widely used to achieve a high hit-rate in modern caches, leading to a considerable enhancement in the system performance. In a conventional set-associative cache, tag and data arrays are simultaneously accessed to achieve fast access, but doing so causes a large amount of energy consumption. Previous attempts, such as way prediction and sequential tag access for energy reduction, are still associated with substantial energy consumption due to the tag access. This paper presents a new cache organization termed Segmented Tag Cache (STC), which reduces the amount of energy consumed during the tag access. The proposed organization initially implements a new tag organization that supports partial tag access. More specifically, the tag array is segmented into two parts, and partial tag access only reads low-order part of the tag. A cache access scheme suitable for the proposed tag organization then are developed. Under the scheme, the delay of the tag organization is hidden by the data access delay, avoiding an increase in the overall cache access time to be maintained. Simulation results show that the STC reduces the energy-delay product by approximately 58 percent compared to the conventional cache organizations with a negligible performance penalty. [ABSTRACT FROM AUTHOR]

A rowhammer error represents a loss of data stored in a DRAM cell caused by electromagnetic interference due to repetitive access to the same and/or adjacent rows. Due to the concentrated occurrence of rowhammer errors in specific rows and columns, these errors cannot be corrected by the conventional error correcting code (ECC) commonly used in DRAM devices. Previous techniques avoid these errors by having additional refresh operations that require additional hardware resources and/or power consumption. This paper proposes a different approach to handle rowhammer errors by distributing them across different DRAM rows and columns so that the attack cells are not concentrated on specific rows and columns. To this end, the distribution of rowhammer errors is observed with experiments using several commercial DRAM devices by employing state-of-the-art rowhammer attack techniques. The observation of the rowhammer errors concentrated in specific rows and columns underlies the proposal of an effective DRAM address remapping scheme for re-distribution of rowhammer errors. By using different address mappings to different chips and arrays in a DIMM, the proposed remapping effectively distributes errors over different rows and columns. As a result, the proposed remapping scheme decreases the possibility of multiple errors in a single word, and consequently, reduces uncorrectable errors under single error or single symbol correcting ECC. Experimental results with commercial DIMMs show that the proposed scheme reduces uncorrectable errors by about 95 percent while incurring a small additional hardware cost. [ABSTRACT FROM AUTHOR]