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We utilize plasma-enhanced atomic layer deposition to synthesize two-dimensional Nb-doped WS2 and NbxW1–xSy alloys to expand the range of properties and improve the performance of 2D transition metal dichalcogenides for electronics and catalysis. Using a supercycle deposition process, films are prepared with compositions spanning the range from WS2 to NbS3. While the W-rich films form crystalline disulfides, the Nb-rich films form amorphous trisulfides. Through tuning the composition of the films, the electrical resistivity is reduced by 4 orders of magnitude compared to pure ALD-grown WS2. To produce Nb-doped WS2 films, we developed a separate ABC-type supercycle process in which a W precursor pulse precedes the Nb precursor pulse, thereby reducing the minimum Nb content of the film by a factor of 3 while maintaining a uniform distribution of the Nb dopant. Initial results are presented on the electrical and electrocatalytic performances of the films. Promisingly, the NbxW1–xSy films of 10 nm thickness and composition x ≈ 0.08 are p-type semiconductors and have a low contact resistivity of (8 ± 1) × 102 Ω cm to Pd/Au contacts, demonstrating their potential use in contact engineering of 2D TMD transistors. [ABSTRACT FROM AUTHOR]

Growing a thick high-quality epitaxial layer on the β-Ga2O3 substrate is crucial in commercializing β-Ga2O3 devices. Metal organic chemical vapor deposition (MOCVD) is also well-established for the large-scale commercial growth of β-Ga2O3 and related heterostructures. This paper presents a systematic study of the Schottky barrier diodes fabricated on two different Si-doped homoepitaxial β-Ga2O3 thin films grown on Sn-doped (001) and (010) β-Ga2O3 substrates by MOCVD. X-ray diffraction analysis of the MOCVD-grown sample, room temperature current density–voltage data for different Schottky diodes, and C–V measurements are presented. Diode characteristics, such as ideality factor, barrier height, specific on-resistance, and breakdown voltage, are studied. Temperature dependence (170–360 K) of the ideality factor, barrier height, and Poole–Frenkel reverse leakage mechanism are also analyzed from the J–V–T characteristics of the fabricated Schottky diodes. [ABSTRACT FROM AUTHOR]

In this paper, we develop an analytic model based on the theory of virtual-source emission-diffusion (VS-ED) to describe ambipolar current conduction in ultrathin black phosphorus (BP) field-effect transistors (FETs). Unlike the VS model which is strictly applicable to quasiballistic devices, the VS-ED model can be applied to long-channel devices with drift-diffusive transport. The model comprehends the in-plane band structure anisotropy in BP, as well as the asymmetry in electron and hole current conduction characteristics. The model also includes the effect of Schottky-type source/drain contact resistances, which are voltage-dependent and can significantly limit current conduction in the on-state in BP FETs. Model parameters are extracted using measured data of back-gated BP transistors with gate lengths of 1000 nm and 300 nm with BP thicknesses of 7.3 nm and 8.1 nm, and for the temperature range 180–298 K. Compared to previous BP models that are validated only for room temperature and near-equilibrium bias conditions (low drain-source voltage), we demonstrate an excellent agreement between the model and data over a broad range of bias and temperature values. The model is also validated against numerical technology computer-aided design data of back- and top-gated BP transistors with a channel length of 300 nm and a thickness of 8.1 nm. The model is implemented in Verilog-A, and the capability of the model to handle both dc and transient circuit simulations is demonstrated using SPECTRE. The model not only provides physical insight into technology-device interaction in BP transistors but can also be used to design and optimize BP-based circuits using a standard hierarchical circuit simulator. [ABSTRACT FROM AUTHOR]

This work reports the quantification of rise in channel temperature due to self-heating in two-terminal SrSnO3 thin film devices under electrical bias. Using pulsed current–voltage (I–V) measurements, thermal resistances of the thin films were determined by extracting the relationship between the channel temperature and the dissipated power. For a 26-nm-thick n-doped SrSnO3 channel with an area of 200 μm2, a thermal resistance of 260.1 ± 24.5 K mm/W was obtained. For a modest dissipated power of 0.5 W/mm, the channel temperature rose to ∼176 °C, a value which increases further at higher power levels. Electro-thermal simulations were performed which showed close agreement between the simulated and experimental I–V characteristics both in the absence and presence of self-heating. The work presented is critical for the development of perovskite-based high-power electronic devices. [ABSTRACT FROM AUTHOR]

The effect of contact gating is studied in high-performance, dual-gated, single-layer (1L) WS2 MOSFETs with semi-metallic Bi contacts. Using a dual-gate geometry, we study the contribution of contact gating in lowering contact resistance, ${R}_{C}$ , by changing the top-gate and bottom-gate voltages independently. The ${R}_{C}$ of the bottom-gated biasing configuration shows ~20x lower contact resistance than the top-gated biasing configuration. ${R}_{C}$ is shown to be strongly affected by the bottom gate voltage, even at fixed channel carrier concentration, and this dependence is shown to be related to modulation of the transfer length by the bottom gate. The results show that despite the importance of semi-metallic materials in improving contact resistance, contact gating is still necessary to achieve ultra-low contact resistance. [ABSTRACT FROM AUTHOR]

A detailed study of gate length scalability and device performance of undoped-body with extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates is presented. The results demonstrated that the improvement of short channel characteristics leads to higher drive current [I.sub.DSAT] and lower extrinsic gate delay CV/I at a fixed OFF-state current [I.sub.OFF].

We propose and demonstrate the use of a β-(AlxGa1–x)2O3 capping layer to achieve increased breakdown voltage, VBR, and VBR2/RON figure of merit in β-Ga2O3 Schottky diodes, where RON is the on-state resistance. We demonstrate that the addition of a 30 nm-thick β-(Al0.22Ga0.78)2O3 cap to an n-type β-Ga2O3 layer grown by metal organic chemical vapor deposition increases the breakdown voltage from 246 to 387 V in diodes with Pt contacts and 3 × 1016 cm−3 n-type doping. The cap increases the surface Schottky barrier with Pt, resulting in reduced carrier injection under reverse bias. The results are in good agreement with simulations which show that the addition of the capping layer enables the peak electric field at breakdown to increase from 2.5 to 3.6 MV/cm. Simulations further show that RON penalty associated with the (AlxGa1–x)2O3 cap can be almost completely eliminated by grading the capping layer. Thus, by raising the barrier height beyond the limit imposed by the metal work function and Fermi level pinning, the proposed heterojunction helps to improve VBR by reducing the reverse leakage current in ultrawide bandgap semiconductor diodes where bipolar doping remains a challenge. [ABSTRACT FROM AUTHOR]

Back-gated, multifinger graphene RF varactors with a de-embedded quality factor frequency product, ${Q} \boldsymbol {\times } {f}$ , above 300 GHz are demonstrated. The effect of different design parameters on the tuning ratio and quality factor at 77 K and room temperature are explored at frequencies between 1 MHz and 18 GHz. The best device has ${Q}$ of 18.4 at 18 GHz. We also perform small signal equivalent circuit modeling on different designs to further explain the effect of design parameters on the RF performance. These results are promising for future integration of graphene varactors in high-speed analog applications. [ABSTRACT FROM AUTHOR]

The radiation tolerance of strained Si/SiGe n-MODFETs is investigated, using 10 keV X-rays, 63 MeV high energy protons, and 4 MeV low energy protons. The effects of radiation exposure on two major device design parameters ([L.sub.SD] and [L.sub.G]) in T-gate Si/SiGe n-MODFETs devices are examined. A strong dependence on source-drain spacing is observed for both the DC and RF characteristics. A drift-diffusion TCAD framework is used for 2-D device simulations. We believe that the low energy protons damage the SiGe/strained-Si/SiGe lattice, leading to partial strain relaxation. The conduction band-offset (CBO) of the strained SiGe/Si heterojunction is lowered leading to higher gate current leakage. The presence of radiation-induced bulk traps in the unrelaxed SiGe layers on the device behavior is also investigated. Index Terms--Bulk traps, buried-channel, displacement damage, MODFET, radiation effects, SiGe, silicon-germanium, strain.

The fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates is possible with the use of wafer bonding and H-induced layer transfer techniques. In Si-on-SiGe-on-insulator (SSOI) MOSFETs, the mobility enhancement of 50% for electrons (with 15% Ge) and 15-20% for holes (with 20-25% Ge) is demonstrated.

Black arsenic phosphorus single crystals were grown using a short-way transport technique resulting in crystals up to 12 × 110 and ranging from 200 nm to 2 thick. The reaction conditions require tin, tin (IV) iodide, gray arsenic, and red phosphorus placed in an evacuated quartz ampule and ramped up to a maximum temperature of 630 °C. The crystal structure and elemental composition were characterized using Raman spectroscopy, x-ray diffraction, and x-ray photoelectron spectroscopy, cross-sectional transmission microscopy, and electron backscatter diffraction. The data provides valuable insight into the growth mechanism. A previously developed b-P thin film growth technique can be adapted to b-AsP film growth with slight modifications to the reaction duration and reactant mass ratios. Devices fabricated from exfoliated bulk-b-AsP grown in the same reaction condition as the thin film growth process are characterized, showing an on-off current ratio of 102, a threshold voltage of −60 V, and a peak field-effect hole mobility of 23 cm2 V−1 s−1 at Vd = −0.9 V and Vg = −60 V. [ABSTRACT FROM AUTHOR]

All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving nonreciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare the effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau--Lifshitz--Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption. [ABSTRACT FROM AUTHOR]

Low-dimensional van der Waals (vdW) materials can harness tightly confined polaritonic waves to deliver unique advantages for nanophotonic biosensing. The reduced dimensionality of vdW materials, as in the case of two-dimensional graphene, can greatly enhance plasmonic field confinement, boosting sensitivity and efficiency compared to conventional nanophotonic devices that rely on surface plasmon resonance in metallic films. Furthermore, the reduction of dielectric screening in vdW materials enables electrostatic tunability of different polariton modes, including plasmons, excitons, and phonons. One-dimensional vdW materials, particularly single-walled carbon nanotubes, possess unique form factors with confined excitons to enable single-molecule detection as well as in vivo biosensing. We discuss basic sensing principles based on vdW materials, followed by technological challenges such as surface chemistry, integration, and toxicity. Finally, we highlight progress in harnessing vdW materials to demonstrate new sensing functionalities that are difficult to perform with conventional metal/dielectric sensors. [ABSTRACT FROM AUTHOR]

We report the results of metal contact resistance, RC, to Nd-doped n-type SrSnO3 films grown by radical-based hybrid molecular beam epitaxy. Sc, Mn, Ti, Al, and Cr contact layers were deposited onto heavily doped SrSnO3 thin films. With no annealing, Al and Cr contacts were found to be highly resistive, while Sc, Mn, and Ti were more conductive, with Mn having the lowest RC of 11 ± 3 Ω-mm, immediately after liftoff. After Al2O3 passivation at 200 °C, Sc, Mn, and Ti contacts all showed Ohmic behavior, with Ti contacts having RC = 2.4 ± 0.3 Ω-mm and a resultant sheet resistance, RS, of 1.66 ± 0.07 kΩ/◻. Specific contact resistivity, ρC, values of 0.03, 0.2, and 0.5 mΩ-cm2 were determined for Ti, Sc, and Mn, respectively. Annealing at 300 °C did not result in any significant change in RC. An additional study was performed using Ti-contacts on bi-layer films consisting of a heavily doped cap layer grown on a moderately doped active layer. It was found that the RC (ρC) of Ti metal to the bi-layer films was ∼1 (2) order(s) of magnitude lower than on single-layer controls. Temperature-dependent analysis was used to extract the barrier height and doping effect for annealed Ti contacts. This work is an important step in evaluating SrSnO3 for use in high-performance and transparent electronic applications. [ABSTRACT FROM AUTHOR]

A SrSnO3 high-frequency field-effect transistor (FET) is demonstrated. The device structure consists of a recessed Schottky-gate FET with a heavily doped cap layer. DC measurements on devices with 0.5- $\mu \text{m}$ gate length and 4- $\mu \text{m}$ source/drain spacing show a maximum drain current of 53 mA/mm and a maximum transconductance of 43.2 mS/mm. Radio frequency (RF) characterization reveals a cut-off frequency, ${f} _{\text {T}}$ , of 1.31 GHz (0.97 GHz) and a maximum oscillation frequency, ${f} _{\text {max}}$ , of 3.25 (3.25) GHz, after (before) de-embedding. These results represent an important advancement in developing perovskite materials for RF applications. [ABSTRACT FROM AUTHOR]

The transfer of chemical vapor deposited (CVD) monolayer graphene by using poly-[4,5-difluoro-2,2-bis-(trifluoromethyl)-1,3-dioxole-co-tetrafluoroethylene] (Teflon AF1600) fluoropolymer (FP) as a sacrificial nanolayer is demonstrated. Owing to the chemical inertness of FPs, the AF1600-assisted transfer produces an ultraclean surface with excellent transfer integrity. Compared with the widely used poly-(methyl methacrylate)-assisted transfer, AF1600-assisted transfer produces better overall transfer quality as measured by root-mean-square (RMS) roughness. Adding a noncovalent surface monolayer between the graphene and the FP facilitates the FP removal after graphene transfer, resulting in a surface with RMS roughness of 0.4–0.5 nm due to a better reduction of the surface residue after transfer. The remaining residue is found to be primarily associated with thermal-expansion ripples in the graphene that act as trapping sites for the low-molecular-weight FP particles. This work provides a scalable solution to clean CVD graphene transfer for many applications, particularly in sensors where surface cleanliness is paramount. The use of prefunctionalized graphene via self-assembled monolayers as molecular scale passivation layer could further enhance its utility as an integration scheme for graphene sensors. [ABSTRACT FROM AUTHOR]

Black arsenic (BAs) is an elemental van der Waals semiconductor that is promising for a wide range of electronic and photonic applications. The narrow bandgap and symmetric band structure suggest that ambipolar (both n- and p-type) transport should be observable, however, only p-type transport has been experimentally studied to date. Here, we demonstrate and characterize ambipolar transport in exfoliated BAs field effect transistors. In the thickest flakes (∼ 80 nm), maximum currents, Imax, up to 60 μA μm−1 and 90 μA μm−1are achieved for hole and electron conduction, respectively. Room-temperature hole (electron) mobilities up to 150 cm2 V−1 s−1 (175 cm2 V−1 s−1) were obtained, with temperature-dependence consistent with a phonon-scattering mechanism. The Schottky barrier height for Ni contacts to BAs was also extracted from the temperature-dependent measurements. Imax for both n- and p-type conductivity was found to decrease with reduced thickness, while the ratio of Imax to the minimum current, Imin, increased. In the thinnest flakes (∼ 1.5 nm), only p-type conductivity was observed with the lowest value of Imin = 400 fA μm−1. Imax/Imin ratios as high as 5 × 105 (5 × 102) were obtained, for p- (n-channel) devices. Finally, the ambipolarity was used to demonstrate a complementary logic inverter and a frequency doubling circuit. [ABSTRACT FROM AUTHOR]

Fabrication of gate-recessed SrSnO3 (SSO) metal-semiconductor field-effect transistors (MESFETs) with Ni Schottky gates is reported on bi-layer epitaxial SSO films with a thin heavily-doped cap layer. Devices with 0.5- $\mu \text{m}$ gate length showed enhancement-mode behavior with a saturation drain current, ${I}_{\text {DSAT}}$ , of 33 mA/mm and peak transconductance, ${g}_{\text {m,max}}$ , of 65 mS/mm. The ${g}_{\text {m,max}}$ value is a roughly $2\times $ improvement over control devices fabricated on single-layer films. Gate-recessed SSO MESFETs with Pt Schottky gates were also explored on the bi-layer films. Devices with 1- $\mu \text{m}$ gate length displayed ${I}_{\text {DSAT}} =133$ mA/mm and $g_{\text {m,max}} =73$ mS/mm, after thermal annealing. [ABSTRACT FROM AUTHOR]

Beta-phase gallium oxide (β-Ga2O3), the most thermally stable phase of Ga2O3, has stimulated great interest in power electronics due to its ultra-wide bandgap (∼4.9 eV) and high breakdown electric field. The relatively low thermal conductivity of β-Ga2O3, however, limits the device performance due to excessive temperature driven by self-heating. Recently, integrating β-Ga2O3 thin films on substrates with high thermal conductivities has been proposed to improve heat rejection and device reliability. In this work, we prepare high-quality single-crystal β-Ga2O3 thin films by mechanical exfoliation of bulk crystals and study their thermal transport properties. Both the anisotropic thermal conductivity of β-Ga2O3 bulk crystals and the thickness-dependent thermal conductivity of β-Ga2O3 thin films are measured using the time-domain thermoreflectance technique. The reduction in the thin-film thermal conductivity, compared to the bulk value, can be well explained by the size effect resulting from the enhanced phonon-boundary scattering when the film thickness decreases. This work not only provides fundamental insight into the thermal transport mechanisms for high-quality β-Ga2O3 thin films but also facilitates the design and optimization of β-Ga2O3-based electronic devices. [ABSTRACT FROM AUTHOR]

A facile, high‐resolution patterning process is introduced for fabrication of electrolyte‐gated transistors (EGTs) and circuits using a photo‐crosslinkable ion gel and stencil‐based screen printing. The photo‐crosslinkable gel is based on a triblock copolymer incorporating UV‐sensitive terminal azide functionality and a common ionic liquid. Using this material in conjunction with conventional photolithography and stenciling techniques, well‐defined 0.5–1 μm thick ion gel films are patterned on semiconductor channels as narrow as 10 μm. The resulting n‐type ZnO EGTs display high electron mobility (>2 cm2 Vs−1) and on/off current ratios (>105). Further, EGT‐based inverters exhibit static gains >23 at supply voltages below 3 V, and five‐stage EGT ring oscillator circuits display dynamic propagation delays of 50 μs per stage. In general, the screen printing and photo‐crosslinking strategy provides a clean room‐compatible method to fabricate EGT circuits with improved sensitivity (gain) and computational power (gain × oscillating frequency). Detailed device analysis indicates that significantly shorter delay times, of order 1 μs, can be obtained by improving the ion gel conductance. [ABSTRACT FROM AUTHOR]

In the first part of this article, a physics-based surface-potential compact model to describe current–voltage (I–V) relationship in few-layered ambipolar black phosphorus (BP) transistors is presented. The proposed model captures the essential physics of thin-film BP FETs by accounting for the effects of: 1) in-plane band-structure anisotropy in BP, as well as the asymmetry in electron and hole current conduction characteristics; 2) nonlinear Schottky-type source/drain contact resistances; 3) interface traps; 4) ambipolar current conduction in the device using two separate quasi-Fermi levels for electrons and holes; and 5) the effect of temperature on the model parameters. In this article, the model is validated against measured data of back-gated BP transistors with gate lengths of 1000 and 300 nm with the BP thickness of 7.3 and 8.1 nm and for the temperature range of 200–298 K. We also validate the model against numerical TCAD data of BP transistors with channel lengths of 300 and 600 nm and BP thickness of 6 nm. The model is also applied to unipolar 2-D FETs with channel materials, such as MoS2 and WSe2. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here shows excellent agreement with experimental and numerical data over broad bias and temperature range. [ABSTRACT FROM AUTHOR]

We report a physics-based surface-potential compact model to describe current–voltage (I – V) relationship in a few-layered ambipolar black phosphorus (BP) transistors. To model the device electrostatics, the 2-D density of states of carriers and Fermi–Dirac statistics are used, while carrier transport is described using the drift-diffusion formalism. The model also comprehends the effects of interface traps and voltage-dependent Schottky-type source/drain contact resistances. Compared with prior BP FET models that are mainly suited for near-equilibrium transport and room-temperature operation, the model developed here is applicable over broad bias and temperature range. Validation of the model against measurement data of BP transistors with gate lengths 300–1000 nm and operating temperature from 200–298 K is demonstrated in a companion article. [ABSTRACT FROM AUTHOR]

We report experimental demonstration of a right-angle black phosphorus (BP) tunneling field effect transistor (TFET). This device utilizes the effective mass anisotropy between the armchair (AC) and zigzag (ZZ) crystal orientations in BP as a means of inducing asymmetry between source and drain tunneling. As a result of this asymmetry, the BP TFET displays a higher ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio by 2 orders of magnitude and steeper SS than BP TFETs oriented along either the AC or ZZ direction only. [ABSTRACT FROM AUTHOR]

Graphene lateral spin valves (LSVs) are promising devices for future memory and magnetic field sensing applications. In this article, we study the dependence of the nonlocal spin resistance, $\Delta {R}_{{\text {NL}}}$ , and the baseline resistance, ${R}_{{\text {BS}}}$ , as a function of the graphene channel width, ${W}$. The scaling trend is quantitatively assessed by using graphene deposited by chemical vapor deposition, which provides a large number of devices with consistent performance. As ${W}$ is scaled from 10 to $0.5~\mu \text{m}$ , the change in $\Delta {R}_{{\text {NL}}}$ matches the theory of contact-induced spin relaxation with a current spin polarization of 3%–5% and a spin diffusion length of $\lambda _{s} = 1.5$ – $2.5~\mu \text{m}$. We also observe a systematic and dramatic decrease in ${R}_{{\text {BS}}}$ , which we attribute to the reduction in charge current spreading. However, we find in the narrowest devices that a small ${R}_{{\text {BS}}}$ remains that arises due to thermoelectric effects, and this trend is confirmed using gate voltage- and charge current-dependent analyses. Finally, we introduce a nonideality factor, ${m} = \vert {R}_{{\text {BS}}} / \Delta {R}_{{\text {NL}}}\vert $ , as a figure of merit to describe the suppression of the baseline relative to the spin signal. In an LSV with ${L} = {1.5}\,\,\mu \text{m}$ , ${W} = {0.5}\,\,\mu \text{m}$ , and n-type conduction, the nonideality factor is as low as ${m} = {0.0252}\,\,\pm \,\,0.0202$ at room temperature showing that nearly ideal bipolar and symmetric spin signals can be achieved in graphene LSVs. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is a promising technology that can be used for low-cost hardware designs. However, SC suffers from its long latency. Although parallel processing can efficiently shorten the latency, duplicated stochastic number generators (SNGs) are necessary, which cause substantial hardware overhead. This paper proposes a scalable SNG based on the spin-Hall-effect (SHE), which is capable of generating multiple independent stochastic streams simultaneously. The design takes advantages of the efficient charge-to-spin conversion from the Spin-Hall material and the intrinsic stochasticity of nanomagnets. Compared to previous spintronic SNGs, the SHE-SNG can reduce the area by $1.6\times -7.8\times $ and the power by $4.9\times -13\times $ while increasing the degree of parallelism from 1 to 16. Compared to CMOS-based SNGs, the proposed SNG obtained $24\times -120\times $ and $53\times $ reduction in terms of area and power, respectively. Finally, three benchmarks were implemented, and the results indicate that SC implementations with the proposed SHE-SNG can achieve $1.2\times -29\times $ reduction of hardware resources compared to implementations with previous CMOS- and spintronic-based designs while scaling the degree of parallelism from 1 to 64. [ABSTRACT FROM AUTHOR]

An ac small signal model for lateral spin valves (LSVs) is developed, and is applied to two different types of devices: spin transmitters and magnetic field sensors. The small signal models explicitly decouple the charge- and spin-dependent components, which describe the intrinsic RC delay and the ac spin accumulation dynamics, separately. The analysis is applied to graphene LSVs as an example to illustrate the optimization strategies for LSV devices. By using the charge-spin circuit model, the scattering parameters and the reflection coefficients at the output terminals are quantitatively calculated as a function of frequency. This model can be used as a guide for future LSV design and to benchmark performance across different material systems. [ABSTRACT FROM AUTHOR]

Precise measurements of the mobility anisotropy along high-symmetry crystal axes in black phosphorus (BP) MOSFETs are reported. Locally back-gated BP MOSFETs with 13-nm HfO2 dielectric and channel length ranging from 0.3 to 0.7 $\mu \text{m}$ are fabricated. A single BP flake of a uniform thickness is exfoliated and etched along armchair (AC) and zigzag (ZZ) crystal axes, and the orientations are confirmed using optical and transmission electron microscopy analyses. The hole and electron mobilities along each direction are extracted using the transfer length method. The AC-to-ZZ hole mobility ratio is found to increase from 1.4 (1.5) to 2.0 (2.9) as the sheet concentration increased from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 at room temperature (77 K). The room-temperature electron mobility anisotropy is found to be similar to that for holes with an AC-to-ZZ mobility ratio increasing from 1.4 to 2.1 from $5.1\times 10^{\textsf {11}}$ to $1.9\times 10^{\textsf {12}}$ cm−2 though electrons showed only a very weak temperature dependence. A Boltzmann transport model is used to explain the concentration- and temperature-dependent mobility anisotropies which can be well described using a charge center scattering model. [ABSTRACT FROM AUTHOR]

The demonstration of SrSnO3 metal–semiconductor field effect transistors (MESFETs) is reported. The device layer structure consists a 28-nm-thick n-type SrSnO3 film on top of an 11-nm-thick undoped SrSnO3 film grown by hybrid molecular beam epitaxy on a (110) GdScO3 substrate. The MESFETs utilize a Pt Schottky gate electrode and diffused Sc Ohmic contacts. A Schottky barrier height of 1.55 eV was extracted for Pt on SrSnO3 using capacitance-voltage measurements. Devices with a gate length of $3~\mu \text{m}$ and source–drain spacing of 9 $\mu \text{m}$ had a drive current of 36 mA/mm at ${V} _{\textsf {GS}} = +1$ V and ${V} _{\textsf {DS}} = +3.5$ V, and a peak extrinsic (intrinsic) transconductance of 17 mS/mm (35 mS/mm). [ABSTRACT FROM AUTHOR]

The many unique properties of graphene, such as the tunable optical, electrical, and plasmonic response make it ideally suited for applications such as biosensing. As with other surface-based biosensors, however, the performance is limited by the diffusive transport of target molecules to the surface. Here we show that atomically sharp edges of monolayer graphene can generate singular electrical field gradients for trapping biomolecules via dielectrophoresis. Graphene-edge dielectrophoresis pushes the physical limit of gradient-forcebased trapping by creating atomically sharp tweezers. We have fabricated locally backgated devices with an 8-nm-thick HfO2 dielectric layer and chemical-vapor-deposited graphene to generate 10× higher gradient forces as compared to metal electrodes. We further demonstrate near-100% position-controlled particle trapping at voltages as low as 0.45 V with nanodiamonds, nanobeads, and DNA from bulk solution within seconds. This trapping scheme can be seamlessly integrated with sensors utilizing graphene as well as other twodimensional materials. [ABSTRACT FROM AUTHOR]

We report high performance, orientation-controlled, and locally back-gated black phosphorus (BP) n-MOSFETs and p-MOSFETs with titanium and permalloy contacts, respectively. Devices with channel length ranging from 0.3 to 0.7~\mu \textm are analyzed. Armchair-oriented BP p-MOSFETs (n-MOSFETs) display 3.5 times (1.5 times) higher maximum current compared with zigzag devices. Saturated transconductance values up to 4.8 times (1.6 times) higher for BP p-MOSFETs (n-MOSFETs) oriented along the armchair direction compared with the zigzag direction are observed. Using this orientation control and contact engineering, n-MOSFETs with transconductance of 110~\mu \textS/\mu \textm and p-MOSFETs with contact resistance as low as 0.31 \textk\Omega \cdot \mu \textm are demonstrated. [ABSTRACT FROM AUTHOR]