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Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here, a simple and scalable material system of conductive oxide interfaces is employed, and their unique properties are leveraged for a new type of resistive switching device. An Al2O3–TiO2‐based valence‐change resistive switching device, where the conductive oxide interface serves both as the bottom electrode and as a reservoir of defects for switching, is demonstrated. The amorphous–polycrystalline Al2O3–TiO2 conductive interface is obtained following the technological path of simplifying the fabrication of the 2D electron gases (2DEGs), making them scalable for practical mass integration. Physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance is combined. The origin of the resistive switching is pinpointed to the conductive oxide interface, which serves both as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence‐change resistive switching devices. The new device, based on scalable and complementary metal–oxide–semiconductor (CMOS)‐technology‐compatible fabrication processes, opens new design spaces toward increased tunability and simplification of the device selection challenge. [ABSTRACT FROM AUTHOR]

One type of thinking needed by engineers is abstract thinking, i.e., higher-order thinking that permits one to solve problems while maneuvering between several levels of complexity (levels of abstraction). In light of the above, the Faculty of Electrical and Computer Engineering (Technion - Israel Institute of Technology) decided to combine two introductory courses, focusing on different levels of abstraction, into a single undergraduate course "Digital Systems and Computer Structure" integrating multiple levels of abstraction, i.e., logical, micro-architecture and architecture levels. The study presented here characterized the attitudes of students and course faculty toward learning and instruction that combine several levels of abstraction. The research, which used quantitative and qualitative tools, involved 103 students and eight teaching staff members. According to the findings, students hold positive attitudes toward learning that incorporates multiple levels of abstraction. both cognitively and affectively, and the correlation between the components is positive, moderate, and significant. Students argue that this type of learning is interesting, provides a complete picture of computer systems, promotes higher-order thinking, and is relevant to industry work. but is also characterized by a high cognitive load. Course faculty claim that teaching that incorporates multiple levels of abstraction is enjoyable, imparts higher-order thinking among students but is very demanding. As for the behavioral aspect, the vast majority of students and instructors prefer learning and teaching that integrate multiple levels of abstraction over those that focus on a few levels. [ABSTRACT FROM AUTHOR]

Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, $2\phi $ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel $2\phi $ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These $2\phi $ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ. [ABSTRACT FROM AUTHOR]

The tunability of conductance states of various emerging nonvolatile memristive devices emulates the plasticity of biological synapses, making it promising in the hardware realization of large‐scale neuromorphic systems. The inference of the neural network can be greatly accelerated by the vector‐matrix multiplication (VMM) performed within a crossbar array of memristive devices in one step. Nevertheless, the implementation of the VMM needs complex peripheral circuits, and the complexity further increases as non‐idealities of memristive devices prevent precise conductance tuning (especially for the online training) and largely degrade the performance of the deep neural networks (DNNs). Herein, an efficient online training method of the memristive deep belief net (DBN) is presented. The proposed memristive DBN uses stochastically binarized activations, reducing the complexity of peripheral circuits, and uses the contrastive divergence (CD)‐based gradient descent learning algorithm. The analog VMM and digital CD are performed separately in a mixed‐signal hardware arrangement, making the memristive DBN highly immune to non‐idealities of synaptic devices. The number of write operations on memristive devices is reduced by two orders of magnitude. The recognition accuracy of 95–97% can be achieved for the MNIST dataset using pulsed synaptic behaviors of various memristive synaptic devices. [ABSTRACT FROM AUTHOR]

Processing-in-memory (PIM) seeks to eliminate computation/memory data transfer using devices that support both storage and logic. Stateful logic techniques such as IMPLY, MAGIC and FELIX can perform logic gates within memristive crossbar arrays with massive parallelism. Multiplication via stateful logic is an active field of research due to the wide implications. Recently, RIME has become the state-of-the-art algorithm for stateful single-row multiplication by using memristive partitions, reducing the latency of the previous state-of-the-art by ${5.1\times }$. In this brief, we begin by proposing novel partition-based computation techniques for broadcasting and shifting data. Then, we design an in-memory multiplication algorithm based on the carry-save add-shift (CSAS) technique. Finally, we develop a novel stateful full-adder that significantly improves the state-of-the-art (FELIX) design. These contributions constitute MultPIM, a multiplier that reduces state-of-the-art time complexity from quadratic to linear-log. For 32-bit numbers, MultPIM improves latency by an additional ${4.2\times }$ over RIME, while even slightly reducing area overhead. Furthermore, we optimize MultPIM for full-precision matrix-vector multiplication and improve latency by ${25.5\times }$ over FloatPIM matrix-vector multiplication. [ABSTRACT FROM AUTHOR]

Y-Flash memristors utilize the mature technology of single polysilicon floating gate nonvolatile memories. It can be operated in a two-terminal configuration similar to the other emerging memristive devices, e.g., resistive random-access memory and phase-change memory. Fabricated in production complementary metal-oxide-semiconductor technology, Y-Flash memristors allow excellent reproducibility reflected in high neuromorphic products yields. Working in the subthreshold region, the device can be programmed to a large number of fine-tuned intermediate states in an analog fashion and allows low readout currents (1 nA ∼ 5 μA). However, currently, there are no accurate models to describe the dynamic switching in this type of memristive device and account for multiple operational configurations. In this paper, we provide a physical-based compact model that describes Y-Flash memristor performance in both DC and AC regimes and consistently describes the dynamic program and erase operations. The model is integrated into the commercial circuit design tools and is ready to be used in applications related to neuromorphic computation. [ABSTRACT FROM AUTHOR]

Currently, data-intensive applications are gaining popularity. Together with this trend, processing-in-memory (PIM)-based systems are being given more attention and have become more relevant. This article describes an analytical modeling tool called Bitlet that can be used in a parameterized fashion to estimate the performance and power/energy of a PIM-based system and, thereby, assess the affinity of workloads for PIM as opposed to traditional computing. The tool uncovers interesting trade-offs between, mainly, the PIM computation complexity (cycles required to perform a computation through PIM), the amount of memory used for PIM, the system memory bandwidth, and the data transfer size. Despite its simplicity, the model reveals new insights when applied to real-life examples. The model is demonstrated for several synthetic examples and then applied to explore the influence of different parameters on two systems -- IMAGING and FloatPIM. Based on the demonstrations, insights about PIM and its combination with a CPU are provided. [ABSTRACT FROM AUTHOR]

A key bottleneck in using phase change memory (PCM) for training artificial neural networks is the abrupt nature of the melt-quench process (amorphization), which does not allow gradual reset. Here we demonstrate analog reset (partial amorphization) in PCM by applying sub-nanosecond programming pulses. Intermediate-level reset states are enabled by reducing the pulse width below the dominant thermal time constant of the PCM, which is on the order of a few nanoseconds. We show gradual change in PCM resistance as a function of number of (sub-ns) reset pulses with 50 intermediate states. Our unique scheme allows fine-tuning the resistance with sub-ns pulses of constant amplitude, which can significantly reduce the programming complexity in training neuromorphic hardware. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is one of the leading candidates for neuromorphic hardware and has recently matured as a storage class memory. Yet, energy and power consumption remain key challenges for this technology because part of the PCM device must be self‐heated to its melting temperature during reset. Here, it is shown that this reset energy can be reduced by nearly two orders of magnitude by minimizing the pulse width. A high‐speed measurement setup is utilized to probe the energy consumption in PCM cells with varying pulse width (0.3–40 nanoseconds) and uncover the power dissipation dynamics. A key finding is that the switching power (P) remains unchanged for pulses wider than a short thermal time constant of the PCM (τth < 1 ns in 50 nm diameter device), resulting in a decrease of energy (E = P × τ) as the pulse width τ is reduced in that range. Thermal confinement during short pulses is achieved by limiting the heat diffusion time. The improved programming scheme reduces reset energy density below 0.1 nJ µm−2, over an order of magnitude lower than state‐of‐the‐art PCM, potentially changing the roadmap of future data storage technology and paving the way toward energy‐efficient neuromorphic hardware. [ABSTRACT FROM AUTHOR]

Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by 1.5× to 4.5×. [ABSTRACT FROM AUTHOR]

Although phase-change materials (PCMs) have been studied for more than 50 years, temperature-dependent characterization of the phase transition dynamics remains challenging due to the lack of nanosecond-nanoscale thermometry. In this article, we utilize the four-terminal, indirectly heated phase-change switch (IPCS), which was originally designed for nonvolatile radio frequency (RF) applications, as an ultrafast electrothermal platform to study PCM. We propose a novel experimental setup that allows nanosecond probing of the transient resistance of the PCM, beyond the melting temperature (>1100 K), due to the built-in electrical isolation between the PCM path and the thermal actuation path of the IPCS. The embedded metallic heater can induce reversible phase transitions between the crystalline and amorphous phases of the PCM. Our platform enables simultaneous measurements of the dynamics of PCM resistance (as a probe for the phase of the material) and heater temperature, during the application of heating pulses. Furthermore, we map the surface temperature of the IPCS at steady state by scanning thermal microscopy (SThM) and show the effect of cooling by electrodes in devices with overlap between the heater and PCM contacts. Our method can be used to study chalcogenides and other amorphous semiconductors for reconfigurable electronics and neuromorphic hardware. [ABSTRACT FROM AUTHOR]

Four-terminal, inline, indirectly heated phase-change switches (IPCS) have emerged as great contenders for reconfigurable radio frequency (RF) integrated circuits, providing state-of-the-art cutoff frequency thanks to their built-in dc-RF decoupling. However, the switching of IPCS devices is determined by their temperature which is challenging to predict. In this article, we present a physics-based compact model of the IPCS, validated by finite-element method simulations and measurements of IPCS devices. The model accurately predicts the thermal and electrical dynamics of the device by considering the changes in heater resistance, contact resistance, and parasitic capacitance. The complete model is implemented in Verilog-A, and a downloadable version is freely available at the nanoHUB.org. We show how the compact model can be used for rapid device evaluation and optimization between RF performance and energy efficiency. Nanosecond electrical thermometry of the heater for varying pulses during IPCS device operation and RF measurements is used to experimentally validate the model. [ABSTRACT FROM AUTHOR]

In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore, a highly motivated objective in modern computer architecture. This article presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed synthesis and in-memory mapping of logic execution in a single row (SIMPLER), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic memristor-aided logic (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory single instruction, multiple data (SIMD) operations. Compared to the previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of 435 ×. When the previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least 5 ×, with 23 × improvement in area and 20 × improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency. [ABSTRACT FROM AUTHOR]

Memristor-aided logic (MAGIC) is a technique for performing in-memory computing using memristive devices. The design of a MAGIC NOR gate has been described in detail, and it serves as the basic building block for several processing-in-memory architectures. However, the input stability of the MAGIC NOR gate forces a limitation on the threshold voltages: the magnitude of the set voltage must be higher than the magnitude of the reset voltage. Unfortunately, many of the current leading resistive switching technologies, particularly, valence change memory (VCM), have the opposite ratio between the threshold voltages. In this article, we experimentally demonstrate the undesirable effects of input instability. Furthermore, we introduce three new MAGIC gates for devices with low set-to-reset voltage ratios and experimentally demonstrate their robust operation using Pt/Ta2O5/W/Pt devices. The three gates, combined with constant values, are functionally complete and are demonstrated as building blocks for in-memory logic on VCM devices. [ABSTRACT FROM AUTHOR]

A non-volatile resistive switching device is demonstrated, utilizing a 2D electron gas (2DEG) between a SrTiO3 substrate and an amorphous Al2O3 layer. A large resistance window is observed, and its origin is discussed. We pinpoint the role of the oxide interface in enabling the resistive switching behavior. The switching mechanism is proposed to be of filamentary type that is formed inside the Al2O3 layer, the result of oxygen vacancies that are driven from the interface into the insulating Al2O3 under high electric fields. These results highlight the concept of memristive devices where the 2DEG serves both as the back electrode and as the source of defects necessary for resistive switching, providing a simple and scalable process for future devices. [ABSTRACT FROM AUTHOR]

Cytomorphic engineering attempts to study the cellular behavior of biological systems using electronics. As such, it can be considered analogous to the study of neurobiological concepts for neuromorphic engineering applications. To date, digital and analog translinear electronics have commonly been used in the design of cytomorphic circuits; Such circuits could greatly benefit from lowering the area of the digital memory via memristive circuits. In this article, we propose a novel approach that utilizes the Boltzmann-exponential stochastic transport of ionic species through insulators to naturally model the nonlinear and stochastic behavior of biochemical reactions. We first show that two-terminal memristive devices can capture the non-linear and stochastic behavior of biochemical reactions. Then, we present the design of several building blocks based on analog memristive circuits that inherently model the biophysical mechanisms of gene expression. The circuits model induction by small molecules, activation and repression by transcription factors, biological promoters, cooperative binding, and transcriptional and translational regulation of gene expression. Finally, we utilize the building blocks to form complex mixed-signal networks that can simulate the delay-induced oscillator and the p53-mdm2 interaction in the cancer signaling pathway. Our approach can provide a fast and simple emulative framework for studying genetic circuits and arbitrary large-scale biological networks in systems and synthetic biology. Some challenges may be that memristive devices with frequent learning and programming do not have the same longevity as traditional transistor-based electron-transport devices, and operate with significantly slower time constants, which can limit emulation speed. [ABSTRACT FROM AUTHOR]

The emerging spin-transfer torque magnetic tunnel junction (STT-MTJ) technology exhibits interesting stochastic behavior combined with small area and low operation energy. It is, therefore, a promising technology for security applications, specifically the generation of random numbers. In this paper, STT-MTJ is used to construct an asynchronous true random number generator (TRNG) with low power and a high entropy rate. The asynchronous design enables the decoupling of the random number generation from the system clock, allowing it to be embedded in low-power devices. The proposed TRNG is evaluated by a numerical simulation, using the Landau–Lifshitz–Gilbert (LLG) equation as the model of the STT-MTJ devices. Design considerations, attack analysis, and process variation are discussed and evaluated. We show that our design is robust to process variation, thus achieving an entropy generating rate between 99.7 and 127.8 Mb/s with 6–7.7 pJ per bit for 90% of the instances. [ABSTRACT FROM AUTHOR]

While DRAM cannot easily scale below a 20-nm technology node, RRAM suffers far less from scalability issues. Moreover, RRAM's resistivity enables its use for processing-in-memory (PIM), potentially alleviating the von Neumann bottleneck. Unfortunately, because of technological idiosyncrasies, existing DRAM-centric memory controllers cannot exploit the full potential of resistive RAM (RRAM). In this paper, we present the design of a memory controller called CONCEPT. The controller is optimized to exploit unique properties of RRAM to enhance its performance and energy efficiency as well as exploiting RRAM's PIM capability. We show that with CONCEPT, RRAM can achieve DRAM-like performance and energy efficiency on SPEC CPU 2006 benchmarks. Furthermore, using RRAM PIM capabilities, we show a 5× performance gain on a data-intensive in-memory database workload compared to a state-of-the-art CPU-memory computing model. [ABSTRACT FROM AUTHOR]

In this paper, a scalable lumped model that accurately predicts the steady-state high-frequency behavior of nanoscale RF memristive devices is presented. The model is described 1) analytically by a set of closed-form equations that determine the parameters based on the device physical structure, allowing for optimized circuit design and performance through structure modifications, and 2) numerically to fit the model parameters to experimental data, allowing for evaluation of the accuracy of the model. This model is, to the best of our knowledge, the first lumped RF memristor model that includes device parasitics obtained from empirical measurements reported in the literature. Results show that the model is reasonably accurate, with 9.6% and 13% relative RMS error for the on-state magnitude and phase, respectively. Furthermore, we propose three topologies (series, shunt, and series-shunt) of nonvolatile single-pole double-throw switches using our lumped RF memristor model. The series and shunt topologies are single-voltage-controlled, while the series-shunt requires two control signals. Simulation results of these topologies exhibit low insertion loss and high isolation (below 0.25 dB and over 63 dB, respectively). The added nonvolatility and nanoscale size will result in reduced power consumption and higher density devices. [ABSTRACT FROM AUTHOR]

Data movement between processing and memory is the root cause of the limited performance and energy efficiency in modern von Neumann systems. To overcome the data-movement bottleneck, we present the memristive Memory Processing Unit (mMPU)-a real processing-in-memory system in which the computation is done directly in the memory cells, thus eliminating the necessity for data transfer. Furthermore, with its enormous inner parallelism, this system is ideal for data-intensive applications that are based on single instruction, multiple data (SIMD)-providing high throughput and energy-efficiency. [ABSTRACT FROM AUTHOR]

Summary: Using memristive devices within a crossbar array could pave the way for memories with higher density and speed than state‐of‐the‐art Flash memory, while maintaining relatively low energy. However, memristive crossbar arrays have great difficulty distinguishing logical states because of sneak path currents. The row grounding technique eliminates the sneak path effect, allowing reliable sampling of the memristor state. In this paper, we analyze the row grounding technique and propose several methods and constraints for the design of memristive crossbar arrays. When the row grounding technique is used for these arrays, our analysis shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays. Simulation results confirm the theoretical analysis proposed in this paper. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In a memristor crossbar array, functioning as a memory array, a memristor is positioned on each row–column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this paper, we study the sneak path problem in crossbar arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are modeling the error channel induced by sneak paths, a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method, we match a constraint on the array content that guarantees sneak-path free readout, determine the resulting capacity, and provide an efficient encoder that achieves the capacity. [ABSTRACT FROM PUBLISHER]

Realizing logic operations within passive crossbar memory arrays is a promising approach to enable novel computer architectures, different from conventional von Neumann architecture. Attractive candidates to enable such architectures are memristors, nonvolatile memory elements commonly used within a crossbar, that can also perform logic operations. In such novel architectures, data are stored and processed within the same entity, which we term as memristive memory processing unit (MPU). In this paper, Memristor-Aided loGIC (MAGIC) family is discussed with various design considerations and novel techniques to execute logic within an MPU. We present a novel resistive memory—the transpose memory, which adds additional functionality to the memristive memory, and compare it with a conventional memristive memory. A case study of an adder is presented to demonstrate the design issues discussed in this paper. We compare the proposed design techniques with the memristive IMPLY logic in terms of speed, area, and energy. Our evaluation shows that the proposed MAGIC design is 2.4 $\times$ faster and consumes 66.3% less energy as compared with the IMPLY-based computing for N-bit addition within memristive crossbar memory. Additionally, we compare the proposed design with IMPLY logic family on ISCAS-85 benchmarks, which shows significant improvements in speed (2$\times$) and energy (10 $\times$), with similar area. [ABSTRACT FROM PUBLISHER]

In recent years, memristive technologies, such as resistive random access memory (RRAM), have emerged. These technologies are usually considered as alternates for static RAM, dynamic RAM, and Flash. In this paper, a novel digital circuit, the multistate register, is proposed. The multistate register is different from conventional types of memory, and is used to store multiple data bits, where only a single bit is active and the remaining data bits are idle. The active bit is stored within a CMOS flip flop, while the idle bits are stored in an RRAM crossbar co-located with the flip flop. It is demonstrated that additional states require an area overhead of 1.4% per state for a 64-state register. The use of multistate registers as pipeline registers is demonstrated for a novel multithreading architecture—continuous flow multithreading (CFMT), where the total area overhead in the CPU pipeline is only 2.5% for 16 threads compared with a single thread CMOS pipeline. The use of multistate registers in the CFMT microarchitecture enables higher performance processors (40% average performance improvement) with relatively low energy (6.5% average energy reduction) and area overhead. [ABSTRACT FROM AUTHOR]

Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to their nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this brief, some applications require voltage-controlled memristors to operate properly. In this brief, a Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage-controlled memristors. The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors. The VTEAM model has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled memristors. The VTEAM model is accurate (below 1.5% in terms of the relative root-mean-square error) and computationally efficient as compared with existing memristor models and experimental results describing different memristive technologies. [ABSTRACT FROM PUBLISHER]

Associative Processor (AP) combines data storage and data processing, and functions simultaneously as a massively parallel array SIMD processor and memory. Traditionally, AP is based on CMOS technology, similar to other classes of massively parallel SIMD processors. The main component of AP is a Content Addressable Memory (CAM) array. As CMOS feature scaling slows down, CAM experiences scalability problems. In this work, we propose and investigate an AP based on resistive CAM—the Resistive AP (ReAP). We show that resistive memory technology potentially allows scaling the AP from a few millions to a few hundred millions of processing units on a single silicon die. We compare the performance and power consumption of a ReAP to a CMOS AP and a conventional SIMD accelerator (GPU) and show that ReAP, although exhibiting higher power density, allows better scalability and higher performance. [ABSTRACT FROM PUBLISHER]

Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, memristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor-aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC nor gate is similar to the structure of a common memristor-based crossbar memory array. A MAGIC nor gate can therefore be placed within memory, providing opportunities for novel non-von Neumann computer architectures. Other MAGIC gates also exist (e.g., and, or, not, and nand) and are described in this brief. [ABSTRACT FROM PUBLISHER]

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study. [ABSTRACT FROM AUTHOR]

In the above article , we wish to add additional information and clarifications regarding the gates and circuits. [ABSTRACT FROM AUTHOR]