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The islanding detection method (IDM) with current disturbance of selected frequency (CDSF) in dc microgrids is gaining extensive attention thanks to its small nondetection zone and good power quality. However, the CDSF is implemented through a positive feedback loop and thus will lead to instability issues for the dc microgrid even in the grid-connected mode. Conventional stabilization control is generally employed on the distributed generator (DG) side and usually requires an additional uninterrupted communication process, which therefore decreases system reliability. In this article, the impedance model of the dc microgrid is established first to reveal the interaction instability mechanism between the voltage source converter (VSC) and DG equipped with CDSF IDM. On top of that, the notch-filter-based active damping method is proposed on the VSC side to avoid amplitude intersection of impedance near the selected resonant frequency, which effectively mitigates the instability caused by the islanding detection loop without relying on communication. Moreover, the parameter design method is further summarized to provide guidance for the selection of notch bandwidth in the proposed damper. In this manner, the stability of the grid-connected system can be improved while the islanding detecting speed is enhanced. In the end, the effectiveness of the proposed stabilizing method is verified by the experiments.

The medium-voltage grid emulator is gaining popularity for testing grid-code compliance of large-capacity converters for renewable energy resources. The cascaded H-bridge converter based on active-front-ends is a promising candidate for high-power grid emulators owing to its high modularity and extendibility. However, the cascaded H-bridge topology-based grid emulator suffers the undesired and unpredictable large dc-link voltage ripple under output voltages with multiple-frequency components, e.g., when emulating the grid voltage flickers and harmonics. In this article, the dc-link voltage ripple characteristics under multi-frequency output conditions are analyzed and a dc-link ripple suppression method adopting harmonic current injection is proposed. The injected current reference is generated by reconstructing the dc-link output current and added to the original active-front-end current control loop. Compared with the existing control methods, e.g., proportional-integral-resonant (PIR), the proposed method has a good voltage ripple suppression effect, especially for multi-frequency outputs. Furthermore, the proposed idea does not need complicated calculation or extra control loops and provides a feedforward reference for the current control, leading to a good dynamic response of dc-link voltage control. Finally, the performance of this suppression control scheme is verified on two 1200 V@40 kW power electronics building blocks of a cascaded H-bridge converter.

In this paper, a sub-module capacitor voltage control (SCVC) is proposed to alleviate the energy balance restriction in the alternate arm converter (AAC). Considering that the arm inductor has a great impact on the energy exchange in AAC, the current commutation modulation is demonstrated firstly in this paper to extend the operating range. Then, the current commutation process for the alternate arms is further explored and derived by analytical expressions. During the commutation process, the current through the turning-on arm is rising, while the contralateral arm current is reversely freewheeling through the diodes of director switches (DSs). Moreover, the mechanism of the capacitor voltage sag caused by commutation process is clarified, which provides the fundamental to design the controller. In this manner, the sub-module capacitor voltage control (SCVC) strategy is further provided to compensate the capacitor voltage sag and achieve the normal operating in the four quadrants. Finally, the simulation and experimental results are both performed to verify the effectiveness of the presented modulation and control strategy in the different conditions.

Due to ultrafast switching speed and high-frequency switching of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (mosfets), crosstalk effect, high turn-on losses and electromagnetic interference are becoming constraints to the efficient and safe applications of SiC mosfets. The split-output structure has attracted widespread attention due to its advantages of overcoming the above constraints by integrating decoupling inductors. Thereby, it fully exploits the potential benefits of SiC mosfets. In this article, the effects of the split inductors on short-circuit characteristics of split-output power module are analyzed. An analytical model of the split-output power module is established to compare the electrical characteristics of the split inductors under normal operation and short-circuit faults. A dedicated short-circuit protection method is proposed based on the detection of the voltage pulse duration across the split inductors. The protection method is validated by hard switching fault and fault under load experiments. The results show that the short-circuit power device can be shut down when the short-circuit current is much lower than the continuous drain current. Besides, the short-circuit energy of the power device has the same order of magnitude as the dissipated energy under normal switching, which avoids degradation and even destruction of SiC mosfets under short-circuit faults.

A 5-to-0.4 $\sim $ 1.2-V reconfigurable capacitive-sigma dc– dc converter with 98.4% peak efficiency is presented. By input-series and output-shunt an efficient unregulated 2:1 switched-capacitor (SC) converter with a reconfigurable hybrid Dickson Buck converter, the proposed converter achieves high efficiency for the entire output voltage and current ranges. Besides, the proposed converter also demonstrates decent regulation and transient responses. The prototype achieved 98.4% and 90.4% peak efficiency at 1.2- and 0.4-V output, respectively. The output shows a static error of 1.1 mV and under-/overshoot voltages of –23 and 23.8 mV with 0.1% settling time of 25 and 30 $\mu \text{s}$ , respectively, over 2-A load range. Compared with the prior state of the arts, the converter improves the peak efficiency by 1.5% at voltage conversion ratio (VCR) = 4.2 and by 4.9% at VCR = 12.5.

The nonuniform large damping introduced by grid-forming (GFM) converters in multi-machine system could destabilize the power system under large disturbance, which may bring new challenges to the safe operation of future power system. In this letter, the mathematic model of GFM-penetrated multi-machine system considering large damping effect is established first, and the concept of uniform and nonuniform damping energy is further proposed to clarify the impact of different damping components. Moreover, the influence mechanism of nonuniform damping on system transient stability is revealed, which implies that the large damping in only part of generators could destabilize the system. The analysis result may provide some new insights for the transient stability analysis of future power system with nonuniform damping effect.

In electric vehicle (EV) inverter systems, the dc-link capacitor bank becomes a critical obstacle to high power density due to its large volume. The dc-link capacitor bank commonly adopts a multicore parallel structure. The challenges exist in the current sharing of parallel capacitor cores because of the imbalance of stray parameters in the busbars. A current sharing analysis method aiming at thermal stress for capacitor banks in high-power-density inverters based on the characteristic matrix is proposed in this article. First, the design basis of dc-link capacitors is given theoretically. Then, the complex coupling impedance model between multiple ports on capacitor busbars is mathematically derived by the matrix method, revealing the current resonance phenomenon of parallel capacitor cores affected by stray parameters. Next, three capacitor banks are evaluated by the proposed current sharing model. The influence of capacitor core arrangement and terminal position on current sharing is explored, which can guide capacitor banks’ high-power-density structure and heat dissipation design. Finally, an experimental platform is built with customized capacitor samples. The experimental results are consistent with the analysis results of the model, verifying the proposed method.

In this article, a multiport network approach is proposed to analyze the forced oscillations issue for the multichips power module. First, experimental results indicate the presence of multiple resonance points caused by forced oscillations during the switching process of multichip power modules. Due to the complex distribution of parasitic parameters within the module, it is challenging to establish an accurate analytical model. Therefore, this article proposes a method based on multisoftware collaborative simulation to extract the corresponding impedance of different chip ports. In addition, the impact of bus parasitic inductance and chip capacitances on port impedance is obtained. Compared with the experimental result, the error of dominant frequency obtained by the proposed model is less than 3%. Furthermore, the sensitivity of the spatial near-field spectrum to bus voltage and load current is studied based on experimental results. Finally, the suppression methods for forced oscillations are proposed based on the aforementioned theoretical analysis from the perspectives of both chips and packaging. The effectiveness of proposed methods is verified through experimental results.

The modularity of the modular multilevel dc-dc converters (MMDCs) makes them a competitive candidate in medium voltage applications but brings the submodule (SM) voltage balancing issue. This article proposes an optimal circulant modulation method for minimizing the SM voltage ripples with inherent balancing capability proven at the same time, which allows smaller SM capacitors and avoids the high-frequency communication for SM voltage balancing. First, the optimal switching pattern is strictly derived providing a general method to theoretically minimize the SM capacitor voltage ripple. Then the switching matrix of the optimal circulant modulation is formulated by introducing the generalized-circulant matrix. It verifies the circularity and full-rank feature of the optimal switching matrix, which promises the uniformity of SM actions and the inherent balancing of SM voltages. Finally, full-scale simulations and down-scaled experiments are both provided with the isolated LLC-based MMDC model and prototype. The results show that the proposed optimal circulant modulation can reduce the SM capacitor voltage ripple by 37% compared with the existed method, and it also promises the inherent SM voltage balancing and SM uniformity.

The damping effect in grid forming (GFM) control is inherently large and thus has great impact on its transient stability. Although qualitative understanding of damping has been developed in recent studies, an analytical and intuitive method for quantitative assessment of damping is still needed to be developed to date. This article visualizes the transient damping energy through the concept of damping area on a tailored phase portrait to physically and intuitively understand the damping effect. On top of that, the damping energy approximation (DEA) method is further proposed to depict transient stability boundary more accurately and evaluate the critical clearing angle analytically. Moreover, the conservativeness of proposed DEA method for GFM converter with both constant terminal voltage control and reactive power-voltage droop control is analyzed in theory and verified in time-domain simulations and control hardware-in-loop experiments. This method quantitatively and visually evaluates the impact of damping on transient stability boundary and critical clearing angle, which avoids complex numerical iterations and may provide some insights into the transient stability analysis of GFM converter.

In this article, a series-connected SiC MOSFETs-based medium voltage (MV) dual active bridge (DAB) converter featuring a low voltage difference among devices and high efficiency is proposed. In the developed DAB converter, the zero voltage switching-on characteristic is used to redesign the voltage balancing snubber circuits of the series-connected SiC MOSFETs. The snubber resistance is greatly reduced, whereas the snubber capacitance is increased, which realizes good voltage sharing and low switching-off loss of SiC MOSFETs. Furthermore, the operating modes and the operating characteristics of MV DAB converter with large snubber capacitors are derived in detail. Based on the above analysis, snubber capacitance and auxiliary inductance are optimized, taking into account the losses and voltage imbalance in the series-connected SiC MOSFETs. Finally, a 4 kV/1 kV experimental prototype is built and tested, and an experiment with up to 100 kW transmission power has been carried out. The results show that a maximum efficiency of 98.7% has been reached and the maximum voltage difference among SiC MOSFETs does not exceed 4%.

Islanding detection based on current disturbance of selected frequency (CDSF) is gaining widespread acceptance in dc microgrids due to its high detecting accuracy and good power quality. However, the selected static disturbance frequency at a specific operating state causes the expansion of the nondetection zone (NDZ) and the decrease of the detection speed under different system power conditions. In this article, the sensitivity model of current perturbation is developed to intuitively reveal the mechanism of oscillation frequency shift and the occurrence of the NDZ. Then, the theoretical resonant frequency is derived to analyze the frequency shift range with the consideration of system power changing, which provides the NDZ boundaries accurately. Moreover, an islanding detection method (IDM) with the adaptive resonant frequency is proposed to provide zero NDZ and fast detection speed by dynamically selecting the most sensitive frequency in different power operating cases. Thus, the conflict between the NDZ and detection speed is effectively addressed. Finally, the effectiveness of the proposed IDM is validated by both the simulations and experimental results.

Medium voltage high-frequency transformer (MVHFT), the key component in a MV solid-state transformer (MVSST), requires high reliability on its insulation parts. With the increase of power density, the insulation design of the MVHFT becomes a big challenge. The transformer needs to ensure both high breakdown (BD) strength for short-term fault tolerance and low partial discharge (PD) for long-term reliable operation. Therefore, beginning with the electric stress analysis and the anti-corona consideration, a mass-manufacturable insulation structure is proposed in this article. In the structure, an improved multishielding structure with an optimized shield potential design is used to reshape the electric field (E-field) distribution for higher BD strength and lower PD. And an end-winding stress grading (SG) method is proposed and modeled for both the structure and the material used. Finally, with the proposed insulation structure, a 100 kW PD free transformer prototype with 75 kV base insulation level (BIL) is built. It passed all insulation tests. Also, the prototype realizes high power density under a high insulation level, which reaches 11.2 kW/L.

This article presents a wide voltage and current range bypass-assist series-capacitor power converter for data centers and automotive applications. The overall power converter consists of a 2:1 charge pump (CP) front stage and a 6-level bypass-assist series-capacitor rear stage, by which the proposed design resolves the troublesome duty cycle limit that a typical series-capacitor converter usually faces. Therefore, the output regulation range is significantly extended and only one inductor is required. Besides, since the converter operates like a simple Buck converter with an equivalent input of $V_{\mathrm {IN}}$ /12, an easy pulse-width-modulation (PWM) and pulse-frequency-modulation (PFM) compatible design is implemented and the efficiency greatly enhanced over a wide load range. The prototype was fabricated using the 180 nm bipolar-CMOS-DMOS (BCD) process and demonstrates a broad operating voltage range of 36~55-V input and 0.6~2.5-V output with 1.5mA~5A load range. For a typical 48-V input, the measured peak efficiencies of 2.5, 1.8, 1 and 0.6-V output are 93.1%, 88.1%, 86.6% and 82.7%, respectively. Additionally, when the load decreases to 30-mA, the proposed converter still achieves efficiencies of 88%, 82%, 80% and 70%, respectively.