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"Global Positioning System (GPS)" is extensively used for various satellite-based navigation applications. Nowadays, a software-defined GPS receiver has been developed since it is low cost, flexible and able to use in developing more advanced navigation processing algorithms. To implement a GPS software receiver, it is necessary to process three main modules: acquisition, tracking and navigation demodulation for the position, velocity and time (PVT) solution. Signal acquisition estimates the two parameters from the incoming satellite signal, and signal tracking keeps track of them as they change in time. These two parameters are the code phase, the delay time between receiver and satellites, and the Doppler frequency shift instigated by the satellites' movement relative to the receiver. This study mainly discusses the operation of signal acquisition and tracking. The theoretical study and simulation of the results are described and tested using MATLAB programming language. The input GPS signal is acquired from an antenna system in GPS and an RF frontend portion. [ABSTRACT FROM AUTHOR]

We present a systematic investigation of the temperature dependent relaxation current behavior for single layer and dual layer Pt metal nanocrystal (MNC)-based Al2O3/SiO2 flash memory gate stacks. Stacks containing single layer Pt MNC exhibit a dual-slope behavior in the log-log plots of the relaxation transient, whereas those with dual layer Pt MNC exhibit a single-slope behavior. We propose a physical model embodying two competing relaxation mechanisms to explain the Pt MNC induced relaxation current-thermionic emission and the quantum tunneling. Based on this model, the dual-slope behavior of single layer MNC-based gate stack can be ascribed to the dominance of thermionic emission at the initial part and quantum tunneling at the tail part. In contrast, the single slope behavior of the dual layer metal nanocrystal-based stack arises from the dominance of the quantum tunneling throughout the relaxation. In addition, we verify that stacks containing dual layer MNC show better retention property than their single layer counterparts. Our results demonstrate that relaxation current measurements offer a simple way to assess the charge retention capability for MNC-based gate stacks. [ABSTRACT FROM AUTHOR]

In this work, we present a comprehensive experimental study of charge loss mechanisms in a dual-layer metal nanocrystal (DL-MNC) embedded high-κ/SiO2 gate stack. Kelvin force microscopy characterization reveals that the internal-electric-field assisted tunneling could be a dominant charge loss mechanism in DL devices that mainly depends on the charge distribution in two MNC-layers and inter-layer dielectric (ILD) thickness between the two layers of nanocrystals. Our findings suggest that an optimized DL-MNCs embedded memory cell could be achieved by defining the ILD thickness larger than the average MNC-spacing for enhancement of retention ability in MNC embedded gate stacks. It implies the possibility of reducing MNC spacing in DL structure of scaled memory devices by controlling the thickness of ILD. [ABSTRACT FROM AUTHOR]

Tri-level resistive switching behavior was observed in an \Al2 \O3/\SiO2 gate stack with Ru metal nanocrystals embedded in the \Al2\O3 layer. The device was successfully switched among three resistance states (high, medium, and low) after a forming process using a simple electrical method. The resistance ratio of the high-resistance state to the low-resistance state is more than \10^3. The insulator-to-conductor (and vice versa) transition of the \Al2\O3 and \SiO2 dielectric layers is elucidated by a physical model, which invokes oxygen ion (\O^2-) trapping/detrapping at the metal–oxide interfaces, as well as \O^2- transport and annihilation with the oxygen vacancies in the breakdown percolation path. The switching transition of each individual dielectric layer is found to be dependent on the polarity of the gate bias. This new understanding opens the prospect of metal-nanocrystal-based \Al2\O3/\SiO2 gate stacks for a resistive switching memory application. [ABSTRACT FROM PUBLISHER]

In this work, we demonstrate a two-step analysis procedure that enables an in-depth understanding of the localized charge trapping and charge decay mechanisms in metal nanocrystal (MNC)-embedded high-κ/SiO2 gate stacks. The results clearly reveal that vertical charge loss and lateral charge diffusion are two competing mechanisms, and they can be identified by discharging current measurements at elevated temperatures and the Kelvin force microscopy characterization. It is found that the MNC with higher work function has a lower inter-dot charge tunneling probability, which is favorable for improved retention in memory applications. However, the vertical charge loss during the initial decay period is a trade-off and it could be minimized by using a dual-layer MNC structure. [ABSTRACT FROM AUTHOR]

Automatic recovery of leakage current to its prestress condition was observed after soft breakdown on Ru metal nanocrystal-based Al2O3/SiO2 gate stack. We propose that the high current density induced upon breakdown causes considerable Joule heating in the breakdown percolation path. This increases the probability of detrapping and thermal diffusion of the oxygen ions which passivates the oxygen vacancies in the percolation path. This recovery mechanism is supported by studies on leakage current and dielectric relaxation current at elevated temperatures. We discuss the significance of our findings in the lights of enhancing the reliability margin of metal nanocrystal-based nonvolatile memory. [ABSTRACT FROM AUTHOR]