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This work concerns high resolution topography characterization at die scale of 28nm FDSOI CMOS technology by interferometric microscopy. It shows that usual test boxes (T-boxes) in scribe line are not representative of the full die topography. Consequently, new parameters are needed in order to take full advantage of high resolution topography characterization at die scale. In that sense, it is observed in this study that coupling full die and die @s ranges can provide new and relevant information about the Chemical Mechanical Polishing (CMP) processes. Moreover, high resolution die topography data makes possible to characterize in-die impact of a structure on its neighborhood and evaluate the pattern density dependency of the CMP processes.

Direct wafer bonding and thinning technologies are now extensively used in combination to produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging demands of new functionalities at the material or device level for 3D integration have allowed increasing the level of maturity of these technologies. This paper will review the physics of wafer direct bonding and its implementation for vertical integration devices of processed strata with vertical interconnects.

The formation of air gaps by means of a non-conformal chemical vapor deposition (CVD) on patterned wafers was successfully demonstrated using SiOC (K=2.9) as inter-level metal dielectric. This paper presents the results on physical characterization and electrical performance evaluation of integrated SiOC air gaps in a three-metal level Cu/SiOC interconnect module. The influence of the air gaps shape on parasitic coupling capacitance between copper lines was also discussed in accordance with mask design rules and processing steps.

A new plasma etch-back planarization technique is presented with countermasking to preplanarize shallow trench isolation (STI) substrates before chemical mechanical polishing (CMP). A preplanarization step is necessary since CMP alone cannot provide effective planarization for sub 0.18 technology due to the dishing effect. The preplanarization step uses the principle of two layer planarization technique which consists of spin coating a first photoresist layer, using a countermask for the lithographic step, flowing and curing the resist blocks in STI topographies, spin coating a second photoresist layer to planarize the residual topography, and transferring the final flat surface into the substrate using conventional plasma etch back. In difference with previous techniques, we used a special mask with oversizing and exclusion of all STI critical dimensions smaller than 1.55 μm, the zones with the smaller STI dimensions being masked using a special narrow lines grid. Such a masking strategy avoids any misalignment problem, where the resized first photoresist blocks are reflowed in STI topographies, leading to an easy planarization by the second resist layer. Additionally, the lithographic step is a noncritical step using conventional i-line resist. Using appropriate planarization model and simulation, the first layer thickness can be adjusted to get an effectively planarized topography. The final surface is then transferred into the oxide substrate using the plasma etch-back technique. Various gas mixtures were tested using LAM 4520 plasma etching equipment. The (Ar/CF4/O2) gas mixture was observed to fulfill etch-back requirements with better performance. Equality of etch rate in resist and in oxide can be adjusted by the O2/CF4 gas ratio. A design of experiment was used to determine the optimum conditions of plasma transfer of the planarized profile into the substrate. Finally, the preplanarized wafer is polished by CMP, resulting in an effectively planarized topography with residual topography smaller than 50 nm. The technique is a noncritical lithographic technique scaleable for technologies below 0.18 μm.

Three-dimensional (3D) technology is the next step in the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Metal bonding might be one of the possible techniques to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure, and ambient air was investigated. At room temperature, a 2.8 J/m 2 bonding toughness was achieved. An electron energy loss spectroscopy spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions vs postbonding annealing were presented with transmission electron microscopy and X-ray diffraction analyses. The ohmic behavior of the bonding was highlighted.