1. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si
- Author
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N. Daix, E. Uccelli, L. Czornomaz, D. Caimi, C. Rossel, M. Sousa, H. Siegwart, C. Marchiori, J. M. Hartmann, K.-T. Shiu, C.-W. Cheng, M. Krishnan, M. Lofaro, M. Kobayashi, D. Sadana, and J. Fompeyrine
- Subjects
Biotechnology ,TP248.13-248.65 ,Physics ,QC1-999 - Abstract
We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.
- Published
- 2014
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