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Matrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression, and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. In-memory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application results in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this article, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input-output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning.

In‐memory computing (IMC) with crosspoint arrays of resistive switching memory (RRAM) has gained wide attention for accelerating machine learning, data analysis, and deep neural networks. By IMC, matrix‐vector multiplication (MVM) can be executed in the crosspoint array in just one step, thus accelerating a broad range of tasks in machine learning and data analytics. However, a key issue for RRAM crosspoint arrays is the forming operation of the memories which limits the stability and accuracy of the conductance state in the memory device. In this work, a hardware implementation of crosspoint array of forming‐free devices for fast, energy‐efficient accelerators of MVM is reported. RRAM devices with a 1.5 nm‐thick HfO2 layer show an initial low resistance without forming and an analogue‐mode programming behavior for high‐accuracy IMC. Accurate hardware MVM is demonstrated by experimental eigenvalue/eigenvector calculation according to the power‐iteration algorithm, with a fast convergence within about ten iterations to the correct solution. Deflation technique and principal component analysis (PCA) enable the classification of the Iris dataset with 98% accuracy compared with floating‐point implementation. These results support forming‐free crosspoint arrays for accelerating advanced machine learning with IMC.

Data-intensive computing applications, such as object recognition, time series prediction, and optimization tasks, are becoming increasingly important in several fields, including smart mobility, health, and industry. Because of the large amount of data involved in the computation, the conventional von Neumann architecture suffers from excessive latency and energy consumption due to the memory bottleneck. A more efficient approach consists of in-memory computing (IMC), where computational operations are directly carried out within the data. IMC can take advantage of the rich physics of memory devices, such as their ability to store analog values to be used in matrix-vector multiplication (MVM) and their stochasticity that is highly valuable in the frame of optimization and constraint satisfaction problems (CSPs). This article presents a stochastic spiking neuron based on a phase-change memory (PCM) device for the solution of CSPs within a Hopfield recurrent neural network (RNN). In the RNN, the PCM cell is used as the integrating element of a stochastic neuron, supporting the solution of a typical CSP, namely a Sudoku puzzle in hardware. Finally, the ability to solve Sudoku puzzles using RNNs with PCM-based neurons is studied for increasing size of Sudoku puzzles by a compact simulation model, thus supporting our PCM-based RNN for data-intensive computing.