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The current challenges of spintronic devices are the large power and long latency for magnetic switching. Current-induced domain wall (DW) motion is a new switching mechanism promising low-power, high-density, and high-speed circuits. It was first studied to build “race track” memory, which is considered as one of the most emerging technologies for future stand-alone memory. Based on the 3-D hybrid integration above CMOS circuits and using magnetic tunnel junction (MTJ) as the write/read heads, DW motion can be advantageously extended to logic and embedded memory applications. In this paper, we present the first DW shift register-based lookup-table circuit to build reconfigurable logic, which may nearly halve the die area compared with conventional SRAM-LUT by sharing a number of subcircuits and suggest some new functions such as multicontext configuration and run-time reconfiguration for further performance improvement. By using a DW electrical model and CMOS 65-nm design kit, its performances such as low power and high computing/reconfiguration speed have been simulated or calculated. [ABSTRACT FROM AUTHOR]

Digital data, generated by corporate and individual users, is growing day by day due to a vast range of digital applications. Magnetic hard disk drives (HDDs) currently fulfill the demand for storage space, required by this data growth. Although flash memory devices are replacing HDDs in applications like mobile phones, laptops, and desktops, HDDs cover the majority of digital data stored in the cloud and servers. Since the capacity growth of HDDs is slowing down, it is essential to look for a potential alternative. One such alternative is domain wall (DW) memory, where magnetic domains in the form of two-dimensional or three-dimensional wires are used to store the information. DW memory (DWM) devices should satisfy the four basic operations, such as writing (nucleating domains or inserting DWs in memory element), storing (stabilizing DWs), shifting (moving DWs), and reading (reading magnetization direction). An external magnetic field or spin-transfer torque can be used to write the information. Spin–orbit torque or electric field may be used for shifting the DWs. The information can be read using tunneling magnetoresistance. The domains may be stored along the tracks using artificial pinning potentials. The absence of moving parts makes the DWM consume less power as compared to HDDs, and be more robust. The potential to stack many layers to store information in three dimensions makes them potentially a large storage capacity device. In addition to memory, DW devices also offer a route for making synaptic devices for neuromorphic computing. Despite these potential advantages of DWM, significant advances in research are needed before DWM could become commercially viable. One of the major challenges associated with DWM is DW dynamics. Many problems, such as controlled DW motion, the stability of domains, reducing the dimensions of the DW devices are still to be addressed. Artificial pinning sites fabricated through either geometrical or non-geometrical methods have been proposed for controlling DW motion. This review paper presents a survey of the investigations carried out so far and the future perspective of such devices. [ABSTRACT FROM AUTHOR]

The magnetic domain is a promising solution for realizing the next-generation information storage, for example, racetrack memory (RM). However, domain nucleation and domain wall (DW) motion are limited by the magnetic tunnel junctions (MTJs) as the write and read heads. Moreover, the size of a single domain limits the further increase in storage density. In this paper, we report a cross structure for efficient magnetic domain manipulations. With the help of voltage control magnetic anisotropy (VCMA) effect and antiferromagnetic/ferromagnetic (AFM/FM) couplings, a fast, low-power, and highly reliable nucleation can be achieved. We also miniaturize the domain size by applying a voltage on the nanowire, increasing the storage density. An optimized RM device is then proposed combining the data detection via the inverse spin Hall effect (ISHE). The proposed device facilitates the development of high-speed, low power consumption, and high-density RM applications. [ABSTRACT FROM AUTHOR]

As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues. [ABSTRACT FROM AUTHOR]

The conventional CMOS transistors reach its power wall due to the increasing leakage current as technology scales down. The spintronic devices show a great promise as one of the alternatives to replace CMOS technology for the next-generation low-power integrated circuits. Recently, the spintronic memory, e.g., spin-transfer torque magnetic random-access memory, has been successfully commercialized. However, the spintronic logic circuits face critical problems and challenges, such as poor direct cascading ability and small operation gain, before practical applications. In this paper, we propose a complementary spintronic logic (CSL) family based on a novel four-terminal spin Hall effect-driven magnetic tunnel junction (FT-SHE-MTJ). Fully electrically separated write/read paths of the proposed FT-SHE-MTJ device can overcome the challenges of direct cascading and operation gain in current spintronic logic circuits. With the aid of a compact model, the functionality and the performance of the proposed CSL circuits are evaluated. Simulation results show that the correct logic fan-out operation can be achieved with a voltage below 150 mV, which is promising for low-power computing. [ABSTRACT FROM AUTHOR]

A multilevel cell (MLC) allows gigabit high-density integration of a spin-transfer torque magnetic random-access memory (STT-MRAM). In this paper, we present an MLC structure based on MgO/CoFeB interfacial perpendicular magnetic anisotropy (PMA) and capping layer adjustment. The effect of capping layer toward interfacial PMA modulation has been investigated by first-principles calculations, which is consistent with the previous experimental results. Two methods have been proposed to realize this STT-MRAM MLC: 1) capping layer thickness and 2) material composition design. Using a physics-based compact model of perpendicular magnetic tunnel junctions, resistance–current curves with four-level resistance states are demonstrated, for which the threshold switching currents with clear separations prove the feasibility of this concept. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work. [ABSTRACT FROM AUTHOR]

Spin transfer torque-based magnetic random access memory (STT-MRAM) is considered as one of the most promising candidates for the next generation of nonvolatile memories; however, its storage density and reliability are currently uncompetitive compared with other nonvolatile memories (e.g., NAND flash). In this paper, a dual-functional memory cell structure, named DFSTT-MRAM, is proposed by stacking multiple magnetic tunnel junctions (MTJs) on top of the CMOS access transistor. In such a structure, the cell can be dynamically configured between two possible functional modes, i.e., high-reliability mode (HR-mode) and multilevel cell mode (MLC-mode), based on the data requirements of the addressed applications. The DFSTT-MRAM cell was electrically modeled based on the perpendicular magnetic anisotropy CoFeB/MgO/CoFeB MTJ integrating the STT stochastic switching behaviors. Transient and Monte Carlo simulations were then performed to evaluate its MLC functionality and reliability performance. Our evaluation results show that the DFSTT-MRAM cell can indeed realize MLC capability providing proper write/read control at the MLC-mode and enhance the intrinsic cell reliability by several orders of magnitude when operating at the HR-mode. This cell structure provides a flexible memory cell design for future advanced applications, such as high-density nonvolatile memory and neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) embedded in complementary metal–oxide–semiconductor (CMOS) has been considered as one of the potentially powerful solutions to build up nonvolatile memory and logic circuits. It possesses many intrinsic merits, such as high speed, instant on/off, good scalability and low-leakage power, and promises to extend the Moore's law. A critical issue in this hybrid MTJ/CMOS structure is the reliable integration of MTJ electric signals to CMOS electronics, especially for the deep submicrometer technology nodes (e.g., 28 nm) in presence of low supply voltage and serious process variations. In this paper, we propose a new sensing amplifier, named separated precharge sense amplifier. This circuit, by separating the discharging and evaluation stages of the sensing operation, can operate at a lower supply voltage (<1.0~V) and reduces the effects of process variations as technology scales, thereby providing higher sensing reliability compared with the previously proposed solutions while preserving the high-speed and low-power consumption. Transient and Monte-Carlo statistical simulations are performed to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I>Ico) and Neel-Brown model (I<0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication. [ABSTRACT FROM AUTHOR]