Search

For autonomous undersea vehicles(AUV), the capacity and reliability of battery packs depend on their range, safety, and overall performance. According to the technical specifications of the energy system of an AUV, the 21700 lithium-ion battery was selected as the unit cell for the battery pack design with the idea of a modular and double-redundant design. A single module can completely use the inner space of the cylindrical battery cabin to improve the capacity of the battery packs, while the structure of multiple modules in series and parallel is convenient for locating faults and carrying out maintenance. Two parallel battery packs can result improved reliability. The test results show that the energy density of the system can reach to 200 Wh/kg and battery packs in modular design have higher energy density, reliability, and maintainability.

In this paper, we propose a good decoding performance, low-complexity, and high-speed decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum-product decoding scheme. To reduce implementation complexity and hardware resource consumption, the messages in the iteration process are uniformly quantified and the function $\Psi (x)$ is approximated with second-order functions. The decoder architecture improves the decoding throughput by using partial parallel and pipeline structures. A modified construction method of parity check matrices was applied to prevent read&write conflicts and achieve high-speed pipeline structure. The simulation results show that our decoder architecture has good performance at signal-to-noise ratios (SNRs) as low as −0.6 dB. We have implemented our decoder architecture on a Virtex-7 XC7VX690T field programmable gate array (FPGA) device. The implementation results show that the FPGA-based LDPC decoder can achieve throughputs of 108.64 Mb/s and 70.32 Mb/s at SNR of 1.0 dB when the code length is 262,144 and 349,952, respectively. The decoder can find useful applications in those scenarios that require very low SNRs and high throughputs, such as the information reconciliation of continuous-variable quantum key distribution.

In a quantum key distribution (QKD) system, privacy amplification (PA) is an essential procedure that can effectively eliminate the leaked information to an eavesdropper and distill a secret key. The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. The implementation of the PA reduces significantly the required number of FPGA Block RAMs. Meanwhile, it automatically adapts to different lengths of input and output blocks. Finally, we verified the correctness and high-speed of the algorithm when implemented in a Xilinx Virtex-7 FPGA.

Quantum key distribution enables unconditionally secure key distribution between two legitimate users. The information-theoretic security is guaranteed by the fundamental laws of quantum physics. Initially, the quantum key distribution protocol was proposed based on the qubits. Later on, it was found that quantum continuous variables can also be exploited for this target. The continuous variable quantum key distribution can build upon standard telecommunication technology and exhibits a higher secret key rate per pulse at a relatively short distance due to the possibility of encoding more than 1 bit per pulse. In this article, we review the current status of the continuous variable quantum key distribution research, including its basic principle, experimental implementations, security and future directions; the experimental progress in this field made by our group is also presented. [ABSTRACT FROM AUTHOR]