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The transient thermal crosstalk between the field-effect transistors (FETs) implemented on a silicon-on-insulator (SOI) substrate is examined. Findings reveal the achievement of a temperature resolution of ~50 mK, a time resolution of 5 ns and a temperature sensitivity of ~0.6 A/K.

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored. Index Terms--Alpha particle, modeling, radiation event, single-event upset, soft error.

The study stated that a general approach, the EQ approach, to assess the scaling potential of nanoscale Si FETs based on both gate control (electrostatics) and quantum confinement. The report stated that with this EQ approach, the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability, while the nonplanar wire structures are significantly better where the effective mass in the confinement direction of the planar MOSFET is relatively small.

Many in the microelectronics field view tunneling field-effect transistors (TFETs) as society's best hope for achieving a >10× power reduction for electronic devices; however, despite a decade of considerable worldwide research, experimental TFET results have significantly underperformed simulations and conventional MOSFETs. To explain the discrepancy between TFET experiments and simulations, we investigate the parasitic leakage current due to Auger generation, an intrinsic mechanism that cannot be mitigated with improved material quality or better device processing. We expose the intrinsic link between the Auger and band-to-band tunneling rates, highlighting the difficulty of increasing one without the other. From this link, we show that Auger generation imposes a fundamental limit on ultimate TFET performance. [ABSTRACT FROM AUTHOR]

Band-to-band tunneling was studied in ion-implanted P/N junction diodes with profiles representative of present and future silicon complementary metal-oxide-silicon (CMOS) field effect transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of capacitance versus voltage characteristics, and compared to secondary-ion mass spectroscopy analysis. When the tunneling current was plotted against the effective tunneling distance (tunneling distance corrected for band curvature) a quasi-universal exponential reduction of tunneling current versus, tunneling distance was found with an attenuation length of 0.38 nm, corresponding to a tunneling effective mass of 0.29 times the free electron mass (m 0), and an extrapolated tunneling current at zero tunnel distance of 5.3× 10 7 A/cm² at 300 K. These results are directly applicable for predicting drain to substrate currents in CMOS transistors on bulk silicon, and body currents in CMOS transistors in silicon-on-insulator. [ABSTRACT FROM AUTHOR]