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Copyright of Traitement Automatique des Langues is the property of Association pour le Traitement Automatique des Langues (ATALA) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Cahiers du Journalisme is the property of University of Ottawa Press and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Countermeasures against side-channel attacks are in general expensive, and a lot of research has been devoted to the optimization of their security versus performance trade-off. Besides, a wide literature has also shown that implementing such countermeasures is an error-prone task and requires to deal with various engineering challenges (e.g., physical defaults, compositional errors,...). This work aims to contribute to this second item, by evaluating the extent to which (almost) key-homomorphic primitives, and in particular a recent PRF instance based on the learning with rounding problem, can lead to easy-to-implement and easier-to-evaluate side-channel-secure designs. We confirm these properties by describing an FPGA implementation that does not require complex (compositional) reasoning in its analysis and can be masked securely under simple design conditions, and for which the evaluation directly scales to arbitrary number of shares. We provide a comprehensive performance and (worst-case) security analysis of our design and compare the obtained results with those of an AES implementation protected with the domain-oriented masking scheme. Results show that simplicity has a cost, which becomes less prohibitive as security requirements increase. [ABSTRACT FROM AUTHOR]

Summary: Noise is an important ingredient for side‐channel‐analysis countermeasures security. However, physical noise is in most cases not sufficient to achieve high‐security levels. As an outcome, designers traditionally aim to emulate noise by harnessing shuffling in the time domain and algorithmic noise in the amplitude domain. On one hand, harnessing algorithmic noise is limited in architectures/devices which have a limited data‐path width. On the other hand, the performance degradation due to shuffling is considerable. A natural complement to operation shuffling is the hardware‐based intra‐cycle shuffling (ICS), which typically shuffles the sample time of bits within a clock cycle (instead of micro‐processor operations). Such architecture eliminates the performance overhead due to shuffling within a single cycle, it is algorithm‐independent, i.e., no need in partitioning of operations, and as it is hardware‐based, the data‐path width can be tailored to better exploit algorithmic‐noise. In this manuscript, we first analyze the noise components in physical designs to better model the algorithmic noise. We then perform an information‐theoretic (IT) analysis of both shuffling countermeasures. The last part of the manuscript deals with real‐world architectures analysis: IT analysis of an Advanced Encryption Standard (AES) core implemented over a 32‐ and 128‐bit wide data‐path embedded with intra‐cycle shuffling and two flavors of shuffling generation (memory‐based and on‐line permutation generation). The manuscript is concluded by underling the benefits which can be achieved with the ICS architecture. [ABSTRACT FROM AUTHOR]

Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A complete analysis of an advanced encryption standard (AES) S-box is conducted using a low-power (LP) 65 nm CMOS technology node. Measurements show that the DDSLL S-box has 35% less power consumption than the static CMOS S-box, with an area increase of only 12%, at the expense of a 2.5x increase in delay which remains fairly acceptable for low-power applications such as RFIDs and smart cards. Also when compared to other dynamic differential logic (DDL) styles, simulation results show that DDSLL and dynamic current mode logic (DyCML) consume the same power which is about 1.8x less that of sense amplifier based logic (SABL). The effect of process variations is also studied, measurement results show that the DDSLL style has lower variability in terms of dynamic power as the activity factor (αF ) is deterministic thanks to glitch-free operation. As for security, the perceived information metric demonstrates that the DDSLL S-box has a 3x security margin compared to static CMOS. Therefore, DDSLL presents an interesting tradeoff between improved security and area constrained low-power designs. [ABSTRACT FROM AUTHOR]

Since their introduction by Kocher in 1998, power analysis attacks have attracted significant attention within the cryptographic community. While early works in the field mainly threatened the security of smart cards and simple processors, several recent publications have shown the vulnerability of hardware implementations as well. In particular, field programmable gate arrays are attractive options for hardware implementation of encryption algorithms, but their security against power analysis is a serious concern, as we discuss in this paper. For this purpose, we present recent results of attacks attempted against standard encryption algorithms, provide a theoretical estimation of these attacks based on simple statistical parameters and evaluate the cost and security of different possible countermeasures. [ABSTRACT FROM AUTHOR]