18 results on '"Su, Hung-Der"'
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2. Hysteresis Effect Induces the Inductor Power Loss of Converter during the Voltage Conversion
3. Ultralow Capacitance Transient Voltage Suppressor Design
4. Demonstration of a HV BCD technology with LV CMOS process
5. Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering
6. Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate
7. A floating well method for exact capacitance-voltage measurement of nano technology
8. 0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V
9. Failure mechanism for input buffer under CDM test
10. Simple scheme to increase hold voltage for silicon‐controlled rectifier
11. Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection
12. The ESD failure mechanism of ultra-HV 700V LDMOS
13. Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure.
14. Bi-Mode Breakdown Test Methodology of Ultrathin Oxide
15. Characteristics of Oxide Breakdown and Related Impact on Device of Ultrathin (2.2 nm) Silicon Dioxide
16. Novel Chip Standby Current Prediction Model and Ultrathin Gate Oxide Scaling Limit
17. High temperature InAs infrared detector based on metal-insulator-semiconductor structure
18. Improving the Electrostatic Discharge Robustness of a Junction Barrier Schottky Diode Using an Embedded p-n-p BJT.
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