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Thyristor control system of the 20 MVar flicker suppressor has been improved essentially. The previous feed forward (FF) loop with each single phase reactive current detector of the MR magnet power supply was exchanged to the present by both FF- and NFB-loops. The FF-loops consists of a three phase reactive power detector of the MPS and a forcing pattern generator on the fast but steady line voltage flicker, sag and surge. The NFB-loops control by the slow parts of the flicker and the unbalanced line voltages. These detectors of the reactive power, the voltage flicker and the unbalance have been developed. Sampled voltage flicker data with 12 bit ADC are processed by Z-80A micro computer system and the forcing pattern is generated by the system through 12 bit DAC into the loop. A typical voltage flicker including sag and surge has been reduced within ± 1.5 %, about 1/3 compared to the previous, at 66 kV primary line.