45 results on '"Temes, G. C."'
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2. Bandpass Delta Sigma A/D convertor using two-path multibit structure
3. Multibit sigma-delta modulator with reduced sensitivity to DAC nonlinearity
4. Multibit oversampled Sigma-Delta A/D convertor with nonuniform quantisation
5. Low-phase-error offset-compensated switched-capacitor integrator
6. A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application
7. A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer
8. Iterative optimization techniques for circuit design
9. High-speed ADC with error correction
10. Part 2: Design, Simulation Techniques, and Architectures for Oversampling Converters: Architectures for High-Order Multibit ΣΔ Modulators.
11. Part 2: Design, Simulation Techniques, and Architectures for Oversampling Converters: DIGITALLY CORRECTED MULTI-BIT ΣΔ DATA CONVERTERS.
12. High-linearity SAR-VCO MASH ΔΣ ADC with second-order noise shaping.
13. Multi-step capacitor-splitting SAR ADC.
14. Comparator-based buffer with resistive error correction.
15. Low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs.
16. Two-step split-junction SAR ADC.
17. Double-sampled ΔΣ modulator with relaxed feedback timing.
18. Dynamic biasing scheme for high-speed/ low-power switched-capacitor stages.
19. Enhanced split-architecture Δ-Σ ADC.
20. Noise-shaped filter implementation.
21. Power efficient noise-coupled ΔΣ ADC with simple delay cells.
22. Wide-band high-accuracy ΔΣ ADC using segmented DAC with DWA and mismatch shaping.
23. Fully passive third-order noise shaping SAR ADC.
24. Passive switched-capacitor filter with complex poles for high-speed applications.
25. Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling and Chopper Stabilization
26. GaAs Differential Amplifiers
27. Correspondence
28. The synthesis of general parameter insertion loss filters using a digital computer
29. An efficient numerical method for the computation of zero- and pole-sensitivities†
30. Efficient technique for excess loop delay compensation in continuous-time ▵ ∑ modulators.
31. Two-step incremental analogue-to-digital converter.
32. Noise-shaping SAR ADC using three capacitors.
33. Accuracy-enhanced switched-capacitor stages using low-gain opamps.
34. Multi-step extended-counting analogue-todigital converters.
35. High-precision switched-capacitor integrator using low-gain opamp.
36. Part 2: Design, Simulation Techniques, and Architectures for Oversampling Converters: MULTIBIT OVERSAMPLED Σ-Δ A/D CONVERTOR WITH DIGITAL ERROR CORRECTION.
37. Switched-R tuning technique for Gm-C filters.
38. Power-up calibration techniques for double-sampling ΔΣ modulators.
39. Improved architecture for low-distortion ΔΣ ADCs.
40. Noise-coupled continuous-time delta-sigma ADCs.
41. Single-loop ΔΣ modulator with extended dynamic range.
42. Efficient floating double-sampling integrator for ΔΣ ADCs.
43. Noise-coupled ΔΣ ADCs.
44. Split-set data weighted averaging.
45. High-speed ΔΣ ADC with error correction.
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