115 results on '"Tran, Xuan-Tu"'
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2. Report on power, thermal and reliability prediction for 3D Networks-on-Chip
3. A low-power, high-accuracy with fully on-chip ternary weight hardware architecture for Deep Spiking Neural Networks
4. How to Develop ECC-Based Low Cost RFID Tags Robust Against Side-Channel Attacks
5. Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags
6. IoT Edge Device Security: An Efficient Lightweight Authenticated Encryption Scheme Based on LED and PHOTON
7. A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs
8. An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture
9. Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices
10. Tiny Neuron Network System based on RISC-V Processor: A Decentralized Approach for IoT Applications
11. A Low-Power CT Second-Order VCO-Based ΔΣADC for Audio Recording on Skywater 130-nm
12. An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection
13. GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks
14. Design and Implementation of a SoPC System for Speech Recognition
15. Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator
16. HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems
17. A Highly Digital VCO-based ADC for IoT Applications on Skywater 130nm
18. Ultra-High-Throughput Multi-Core AES Encryption Hardware Architecture
19. A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications
20. A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction
21. A proposal for enhancing training speed in deep learning models based on memory activity survey
22. A Review of Algorithms and Hardware Implementations for Spiking Neural Networks
23. A wideband high dynamic range triple‐stacked FET dual‐shunt distributed analogue voltage controlled attenuator
24. Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture
25. A Lightweight AEAD encryption core to secure IoT applications
26. A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks
27. An Implementation of PCA and ANN-based Face Recognition System on Coarse-grained Reconfigurable Computing Platform
28. Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)
29. A thermal distribution, lifetime reliability prediction and spare TSV insertion platform for stacking 3D-ICs
30. 2D Parity Product Code for TSV online fault correction and detection
31. Thermal distribution and reliability prediction for 3D Networks-on-Chip
32. An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder
33. TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems
34. Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks
35. A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip
36. FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices
37. A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems
38. An Efficient Implementation of LED Block Cipher on FPGA
39. 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults
40. A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization
41. A Survey of High-Efficiency Context-Addaptive Binary Arithmetic Coding Hardware Implementations in High-Efficiency Video Coding Standard
42. An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs
43. A Variable Precision Approach for Deep Neural Networks
44. A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications
45. An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks
46. High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages
47. TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects
48. An Adaptive and High Coding Rate Soft Error Correction Method in Network-on-Chips
49. A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G Wireless Communications
50. A Reconfigurable Multi-function DMA Controller for High-Performance Computing Systems
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