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Nano-sized unmanned aerial vehicles (UAVs) have been attracting growing attention from both academia and industry with their compact and versatile nature. With the size of merely several centimeters, they are particularly well-suited for executing targeted missions in confined spaces, such as tracking a single pedestrian indoors. However, due to strict constraints on payload and power consumption, the onboard computing unit of nano-UAV is limited to the microcontroller Unit (MCU), which makes the novel single object tracking algorithms not applicable on nano-UAV platform. In this paper, we present a lightweight single pedestrian tracking algorithm to meet the strict resource constraints of nano-UAV system. The algorithm consists of an object detection frontend and a motion-based tracking backend. Based on our deployment methodology, covering from dataset production, model training to layer fusion and deployment, the proposed algorithm achieves extreme complexity reduction (13 × fewer operations and 106 × less memory), and keeps good tracking performance compared with state-of-the-art (SOTA) research work. The full range of onboard experiments illustrate the efficiency our algorithm for real-time tracking (up to 43 fps). Meanwhile, both high computing efficiency (5.2 MACs/cycle) and energy efficiency (5.3 mJ/frame) are achieved and exceed similar works on nano-UAV. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of the architecture of a fraction phase based frequency calibration unit where the number of delay cells (that sense the fraction phase) have been reduced to zero. As no pre-calibration of the delay values are required, it becomes immune to process-voltage-temperature variation. Simulation results for frequency convergence have been provided for different target frequencies of an LC oscillator and for an accuracy of 400 ppm. The paper next presents the design and analysis of a voltage controlled oscillator in the form of an astable multivibrator that is similar to a single stage ring oscillator. A novel resistive tuning technique that occupies small chip area and provides less process variation and more matching has been proposed. Also, it has been shown that although the oscillator's phase noise is worse than LC oscillator, the frequency convergence probability (when using the frequency calibration unit with 4 delay cells, due to the high jitter values) does not degrade significantly with the same calibration unit specifications. Hence successful integration of the oscillator with the calibration unit is possible with the advantage of having fully on-chip design with lower power consumption than that of LC oscillators. The oscillator and the calibration circuit have been designed in UMC 180 nm technology that together consume a current of 320µA (in simulation) from 1.6 V power supply. The designs have been targeted for implant telemetry in the 402–405 MHz band having the requirement of ultra low power consumption. [ABSTRACT FROM AUTHOR]

This letter presents the first duty-cycled low-noise amplifier (LNA) operating in the V-band (40–75 GHz). The amplifier employs a two-stage cascode topology and focuses on low power consumption and therefore fast settling times. The switching is achieved by using inverters at the common-gate (CG) transistor of the cascode stage. This control technique enables adapting the duty-cycle and, therefore, the data rate depending on the required performance. The LNA can be operated in an oversampling mode fulfilling a wake-up function and consuming only 22 μW for a data rate of 294 kb/s or in continuous mode dissipating 3.6 mW. A settling time of 0.6 ns, a rise time of 19 ps, and a fall time of 27 ps have been experimentally demonstrated on a prototype fabricated in a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology. The measurement results include a peak gain of 18 dB, a 3-dB bandwidth of 18 GHz, an average noise figure (NF) of 4.9 dB within the 3-dB band, and an input 1 dB compression point (P1dB) at 60 GHz of −21.1 dBm. [ABSTRACT FROM AUTHOR]

High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%. • Identified the most power efficient FPGA tile. • Studied the performance and logic capacity tradeoff in different FPGA tiles. • Identified robust look-up-table designs for operating under limited power budget. • Showed the importance of using level converters in power-constrained FPGAs. [ABSTRACT FROM AUTHOR]

In this paper, a Bulk Driven Gain Boosting (BDGB) technique has been analyzed which is further employed in the design of a novel operational amplifier to enhance the gain and at the same time, a nested compensation technique is also used to improve the bandwidth without consuming extra power. The proposed operational amplifier circuit has been designed in sub threshold region and is biased with very less current at the first stage; an extra biasing circuit with gate to drain connected transistors is also designed to bias the last stage. The proposed configuration achieves open loop gain of 70dB, CMRR of 144dB, PSRR of 70dB and the unity gain bandwidth of 11MHz at 5pF load capacitance. The output swing is more than 650mV at 0.8V supply voltage consuming only 2.5µW static power. The gain/swing performance of the proposed low-voltage OPAMP would be therefore good enough not to require another amplifying stage in many high-speed, high swing and low-power applications. [ABSTRACT FROM AUTHOR]

A dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect, process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of power, delay, noise and robust against parameter and process corner variations. [ABSTRACT FROM AUTHOR]

Highlights • A refined artificial axon-hillock neuron circuit is proposed. • A down-scaling of supply voltage (200 mV), transistors width (120 nm) and feedback capacitance (5 fF) is applied. • The circuit is realized in industrial TSMC 65 nm technology. • Its standby power consumption (11 pW) and energy efficiency (2 fJ/spike) are state-of-the-art. Abstract Artificial Intelligence (AI) applications are developing at a high rate, facing soon a tremendous energy challenge. In this context, the original Axon-Hillock (AH) Artificial Neuron (AN) has been optimized to achieve ultra-low power (ULP) consumption. The membrane capacitance was taken out, and in order to drastically reduce its power consumption, the (feedback) capacitance is lowered to 5 fF, the transistors gate width is reduced to 120 nm and the supply voltage is decreased to as low as 200 mV. Designed and fabricated using 65 nm CMOS Technology, the refined AH neuron features a standby power of 11 pW, and when excited, a power consumption that does not exceed 30 pW for a firing frequency of 15.6 kHz. Its energy efficiency per spike is lower than 2 fJ/spike when the DC power is included (around 1 fJ/spike excluding the DC power), for an area of 31 µm2. These performance confer to this ULP AH neuron a high potential for future development of highly energy efficient Spiking Neural Networks, required to design future neuroprocessors embedded in various applications (smart visual sensors for autonomous vehicles, robotics). [ABSTRACT FROM AUTHOR]

• 2 Transistor negative capacitance inverter requires less transistor count to exhibit hysteresis. • Hybrid Schmitt trigger configurations suffer from difference in NDR and strengths of n- and p-sub-circuits. • Accurate approach to model hysteresis window and minimum supply voltage has been developed. • MFMIS NCFETs can lower the V dd requirement for sustaining hysteresis in Schmitt trigger. • Negative capacitance FET based Schmitt trigger outperforms other topologies because of enhanced feedback made possible through a higher on-to-off current ratio. Through an analytical framework, the work showcases the potential benefits of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) negative capacitance (NC) transistor (T) to enhance the hysteresis width (Δ V H) and reduce the minimum supply voltage (V dd,min) of ultra low power (ULP) subthreshold Schmitt trigger (ST) at shorter gate lengths. Analyzing different ST configurations i.e. 2T (both NCFET), 4T-hybrid (realized through combination of NCFETs and MOSFETs), and 6T (all NCFETs or MOSFETs), leads to the inferences that (i) an inherent negative differential resistance of NCFET can be utilized for hysteresis in 2T-ST circuit, (ii) 4T-hybrid ST is not beneficial for enhancing Δ V H due to a current mismatch between MOSFET and NCFET, and (iii) an optimized 2T-ST and 6T-ST designed with high-permittivity (κ) sidewall spacer (Si 3 N 4) and ferroelectric layer (6 nm) can function at V dd,min of ∼ 55 mV, and ∼ 39 mV, respectively. Results indicate towards potential benefits of realizing ULP subthreshold ST through MFMIS NCFETs without any circuit overhead. [ABSTRACT FROM AUTHOR]

This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an LC oscillator, an envelope detector and a base-band amplifier. To optimize the trade-off between RF performances and power consumption, the cross-coupled based oscillator is biased in moderate inversion region. The proof of concept is implemented in a 65 nm CMOS technology and is intended for the 2.4 GHz ISM band. With a supply voltage of 0.5 V, the demodulator consumes 120 μW and demonstrates the demodulation of OOK and FSK at a data rate of 500 kbps.

This paper presents an electrocardiogram (ECG) processor on chip for full ECG feature extraction and cardiac autonomic neuropathy (CAN) classification. Full ECG extraction is performed using absolute value curve length transform (A-CLT) for $\text{QRS}_{\text{peak}}$ detection and using low-pass differentiation for other ECG features such as $\text{QRS}_{\text{on}}$ , $\text{QRS}_{\text{off}}$ , Pwave, and Twave. The proposed QRS detector attained a sensitivity of 99.37% and predictivity of 99.38%. The extracted $\text{QRS}_{\text{peak}}$ to $\text{QRS}_{\text{peak}}$ intervals (RR intervals) along with QT intervals enable CAN severity detection, which is a cardiac arrhythmia usually seen in diabetic patients leading to increased risk of sudden cardiac death. This paper presents the first hardware real-time implementation of CAN severity detector that is based on RR variability and QT variability analysis. RR variability metrics are based on mean RR interval and root mean square of standard differences of the RR intervals. The proposed architecture was implemented in 65-nm technology and consumed 75 nW only at 0.6 V, when operating at 250 Hz. Ultralow power dissipation of the system enables it to be integrated into wearable healthcare devices. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET's steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has 91% smaller energy delay product (EDP) and 84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2V VDD. [ABSTRACT FROM AUTHOR]

For transiently powered systems a reliable power management is essential. Power management methods in software allow for run-time decisions about the utilization of system resources based on energy models, performance counters and sensor readings. However, finding precise energy models for peripheral devices can become a tedious and challenging task, as they are subject to hardware/software interactions and complex hardware behavior, often with unknown energy characteristics. In this paper, we tackle these problems for a broad set of cases by creating an automated measurement loop for deriving precise energy costs of driver function calls and their parameters. This becomes possible by using an automata-based modeling scheme, which can easily be implemented into the system software. [ABSTRACT FROM AUTHOR]

In this work, an ultra low power all-MOSFET based current reference circuit, developed in 0.18 µm CMOS technology, is presented. The proposed circuit is based on the classical resistor-less beta multiplier circuit with an additional temperature compensation feature. The circuit is capable of providing the reference current in a nanoampere range for the supply voltage ranging from 1 V to 2 V in the industrial temperature range of −40 °C to 85 °C. The measurements were performed on 10 prototypes. The measured mean value of the reference current is 58.7 nA with a mean temperature coefficient value of 30 ppm/°C. In addition, the measured mean line regulation is 3.4%/V in the given supply voltage range. The total current consumption of the circuit is 352 nA and the chip area is 0.036 mm 2 . [ABSTRACT FROM AUTHOR]

The development of ultra-low-power (ULP) electronic devices has opened up opportunities for disruptive systems like the Internet of Things (IoT). The main concern is the security and privacy issues of the huge amount of personal, sensitive, or safety-related data being processed in these systems. Ensuring security in these ULP systems poses additional challenges than in computers, because of power and cost constraints and physical accessibility by attackers. To solve these problems, innovations in both software and hardware are needed. This article presents a survey of state-of-the-art hardware designs optimizing the tradeoffs between security, power, and costs (including design and manufacturing). The authors analyze the connections between hardware specs and system demands to bridge the gap between research conducted in different communities. They also identify open problems in designing future ULP secure hardware. [ABSTRACT FROM AUTHOR]

Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here. [ABSTRACT FROM AUTHOR]

A low-power low-voltage CMOS receiver architecture with a combined LNA-VCO-mixer structure is proposed. An inversion-coefficient (IC) based design procedure is presented that facilitates finding a power-efficient operating point for the low-noise amplifier (LNA) and the voltage-controlled oscillator (VCO) blocks. At the architecture level, the bias currents of LNA and mixer are combined, filtered, and reused for the VCO. This approach facilitates lowering the supply voltage and improves the power efficiency of the system. As a proof of concept, a 2.4 GHz receiver suitable for wireless sensor network applications is designed and fabricated in a 0.13-µm CMOS process. The receiver has an intermediate frequency (IF) of 50 MHz. The RF-to-IF gain of the receiver is 30.1 dB and its noise figure (NF) is 8.3 dB. The combined LNA-VCO-mixer receiver consumes 510 µW from a 0.8-V supply. [ABSTRACT FROM AUTHOR]

Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID) design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

This study investigates the benefit of an optimal and energy-efficient reconfiguration technique for the design of channel-aware receiver aiming Internet of Things (IoT) applications. First, it demonstrates the interest for adaptive receivers based on an estimation of the received power and compares the proposed channel-aware receiver with the State Of the Art. It is shown that the lifetime of the Wireless Sensor (WS) battery can be extended by a factor of five with the optimization of operating points of the tunable receiver while maintaining similar performances than industrial modules. The design of an Ultra-Low Power (ULP) inductorless Low Noise Amplifier (LNA), which fits the low power mode of the tunable receiver, is then optimized and described. The back-gate biasing of Fully Depleted Silicon-On-Insulator (FD-SOI) technology to lower the power consumption by more than 25% still maintaining performances is evaluated. The proposed LNA has been implemented in ST-Microelectronics 28 nm FD-SOI Technology, its active area is only 0.0015 mm2. The measured performances at 2.4 GHz exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF), and a −16 dBm Input referred third-order Intercept Point (IIP3). The LNA consumes 300 µW from a 0.6 V supply.

In current bulk CMOS technology, semiconductor devices are continuously scaled down to achieve higher speed and packing density. This continuous scaling of MOSFET below 45nm technology node gives rise to short channel effects like DIBL, Vt roll off, random dopant fluctuations, mobility degradation etc. There is a need to explore devices beyond bulk CMOS that exhibits higher ION/IOFF ratio, scalability, better channel electrostatics and robustness against process variations. Tunnel Field Effect Transistor (TFET) is considered as one of the most promising device to provide scaling benefits with significant reduction in short channel effects. This paper presents a comparative study of CMOS and TFET based Second Generation Current conveyor (CCII) at a supply voltage of ±0.3V and bias current of 1nA at 32nm technology node. The performance parameters of CCII have been investigated in terms of current gain (α), voltage gain (β), current and voltage bandwidths, resistances and their respective bandwidths at various ports of CCII. It has been found that there is considerable improvement in most of the above parameters using TFET. [ABSTRACT FROM AUTHOR]

Wireless sensor networks (WSNs) have received significant attention in recent years and have found a wide range of applications, including structural and environmental monitoring, mobile health, home automation, Internet of Things, and others. As these systems are generally battery operated, major research efforts focus on reducing power consumption, especially for communication, as the radio transceiver is one of the most power-hungry components of a WSN. Moreover, with the advent of energy-neutral systems, the emphasis has shifted toward research in microwatt (or even nanowatt) communication protocols or systems. A significant number of wake-up radio receiver (WUR) architectures have been proposed to reduce the communication power of WSN nodes. In this work, we present an optimized ultra-low power (nanowatt) wake-up receiver for use in WSNs, designed with low-cost off-the-shelf components. The wake-up receiver achieves power consumption of 152 nW (with -32\,\text dBm sensitivity), sensitivity up to -55\,\text dBm (with maximum power of 1,2 \upmu\text W), latency from 8\;\upmu\texts, tunable frequency, and short commands communication. In addition, a low power solution, which includes addressing capability directly in the wake-up receiver, is proposed. Experimental results and simulations demonstrate low power consumption, functionality, and benefits of the design optimization compared with other solutions, as well as the benefits of addressing false positive (FP) outcomes reduction. [ABSTRACT FROM PUBLISHER]

This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an LC oscillator, an envelope detector and a base-band amplifier. To optimize the trade-off between RF performances and power consumption, the cross-coupled based oscillator is biased in moderate inversion region. The proof of concept is implemented in a 65 nm CMOS technology and is intended for the 2.4 GHz ISM band. With a supply voltage of 0.5 V, the demodulator consumes 120 μW and demonstrates the demodulation of OOK and FSK at a data rate of 500 kbps. [ABSTRACT FROM AUTHOR]

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3-2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0-100°C which is suitable for most of the biomedical sensing applications. [ABSTRACT FROM AUTHOR]

Although class D amplifiers (CDAs) are highly advantageous over their linear amplifier counterparts in terms of power efficiency, their power efficiency remains undesirably low at nominal operation conditions where the output power is $\sim$26 dB lower than its peak output power (due to the large crest factor of the audio/speech signal and headroom for adjustment). This is particularly the case for power-critical micropower applications such as hearing instruments. At nominal conditions, we find that the overcurrent protection circuit (for the output stage) is unexpectedly the most power-dissipative block in micropower CDAs. In this brief, we propose a novel ultralow-power overcurrent protection circuit, which features 67% lower power dissipation compared to conventional overcurrent protection circuit without compromising the IC area. To further verify the advantages of the proposed overcurrent protection circuit, an ultralow-power bang–bang CDA is designed. We show that, by employing the proposed overcurrent protection circuit, the power efficiency of the bang–bang CDA is significantly improved from 10.5% to 23.7% for a 64- $\Omega$ load and from 1.8% to 4.7% for a 400- $\Omega$ load. [ABSTRACT FROM AUTHOR]

This paper reports on the design and experimental realization of a dual-mode surface acoustic wave (SAW) resonator with two high-impedance resonant peaks for ultra low power binary frequency-shift-keying (FSK) modulator applications. The single-device structure of the dual-mode resonator is believe to be a promising solution to eliminate the loading effect and noise as a result of multiple switches and other parallel connected resonators, and has the potential to reduce the size and complexity of packaging, compared with the multi-resonator multi-frequency approaches. The dual-mode SAW resonator concept is realized by an in-house, two-mask process that delivered symmetric-mode resonators at 404.9 MHz with trans-impedance values of 1,100 Ω and quality factor of 3134, and anti-symmetric mode resonators at 407.6 MHz, with 900 Ω trans-impedance and 4014 quality factors. Based on the experimental results, we propose a FSK modulator that integrates this high-transimpedance dual-mode resonator and reaches data rates up to 1.5 Mbps. The FSK modulator can be used for low power transmitters in body area network (BAN) and wireless sensor networks (WSN). [ABSTRACT FROM AUTHOR]

A combined low-noise amplifier and voltage-controlled oscillator (LNA-VCO) is implemented in a 0.13-µm CMOS technology. The low-power LC VCO and LNA circuits are stacked and share the same bias current. An LC filter is used between the LNA and the VCO to improve the isolation between the two functions. Based on the measurement results of the proof-of-concept prototype, the LNA achieves a gain of 18.4 dB and a noise figure (NF) of 3.8 dB at 2.4 GHz. The VCO has a center frequency of 2.45 GHz with a −5.3 dBm output power and a phase noise of −119 dBc/Hz at 1-MHz offset. The combined LNA-VCO block consumes 240 µW from a 0.8 V supply. [ABSTRACT FROM AUTHOR]

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 µm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in $$0.13 \,\upmu \hbox {m}$$ CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only $$113\, \upmu \hbox {W}$$ during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved. [ABSTRACT FROM AUTHOR]

In this paper, a new ultra-low-voltage ultra-low-power operational trans conductance amplifier (OTA) using feedforward technique is proposed. The proposed topology is based on a bulk driven input differential pair employs a gain-stage in the Miller capacitor feedback path to improve the pole-splitting effect. In addition, through a coupling capacitance, input signal is simultaneously coupled to gate of idle transistors resulted dramatic enhancement in gain and unity gain-bandwidth (UGB) of the OTA. The circuit is designed in the 0.18µm CMOS technology. The simulation results show that the amplifier has a 90dB open-loop DC gain and a unity gain-bandwidth of 270 kHz while operating at 0.5V supply voltage. This technique show remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair technique. The total power consumption is as low as 900nW which makes it suitable for low-power bio-medical applications. [ABSTRACT FROM AUTHOR]

A fully integrated low-noise amplifier (LNA) with 0.4V supply voltage and ultra-low power consumption at 1.5GHz by folded cascode structure is presented. The proposed LNA is designed in a TSMC 0.18 μm CMOS technology, in which the all transistors are biased in sub-threshold region. Through the use of the proposed circuit for the gain enhancement in this structure and using forward body bias technique, a very high figure of merit is achieved, in comparison to the similar structures. The LNA provides a power gain of 14.7bB with a noise figure of 2.9dB while consuming only 790μW dc power. Also, the impedance matching of the input and output circuit in its operating frequency is desirable and in the whole circuit bandwidth, input and output isolation is below -33dB. [ABSTRACT FROM AUTHOR]

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-of-the-art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 μW from a 0.3-V supply. [ABSTRACT FROM AUTHOR]

In this paper, a robust sub-threshold 13 T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8 Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents an analysis of energy dissipation of a decimation filter chain of four Half Band Digital (HBD) filters operated in the sub-threshold (sub-V T) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65nm CMOS technology with low-power and three threshold options, both as single-V T and as dual-V T. A sub-V T energy model is applied to characterize the designs in the sub-V T domain. Simulation results show that the unfolded by two and four architectures are the most energy efficient for throughput requirements between 250k samples/s, and 2M samples/s. By the selection of optimum architectures and standard cells, at the required throughput the simulated minimum energy dissipation for the required throughput per output sample is 164fJ and 205fJ, with single supply voltage of 260mV. [Copyright &y& Elsevier]

Abstract: This paper describes an ultra low power receiver RF front-end to be utilized for wireless sensor network (WSN) applications. The design of the LV cell (LNA and VCO) that is proposed in this paper is suitable for direct conversion architecture, while the conventional LMV cell (LNA, Mixer, and VCO) is used only in low-IF architectures, due to the prohibitive high flicker noise. A passive mixer is utilized instead of an active mixer and a capacitor is added to block the DC current flowing into the mixer. So, flicker noise corner frequency is reduced to 13.8kHz. The proposed design can be used more easily compared to conventional LMV cell in a low voltage technology, because of the stacking of only two blocks (LNA and VCO), while three blocks of LNA, mixer, and VCO are stacked in the conventional LMV cell. The proposed receiver RF front-end consumes 1mW in 0.18μm CMOS technology with a 1.2V supply source. NF and IIP3 are 4.7dB and −7dBm, respectively. [Copyright &y& Elsevier]

In order to reduce the power consumption of RFID tags and increase the reading range of RFID systems, this paper proposes an ASK demodulator that uses a new approach to reduce the threshold voltage of diode connected MOS transistors as an obstacle in the design of the envelope detector. Also, an ultra low power comparator is used for further power reduction. This circuit has been simulated in a 0.18 μm CMOS technology to satisfy EPC Class 1 Generation 2 standard protocol emphasizing on the reduction of power consumption. The proposed circuit can correctly demodulate the minimum input RF signal amplitude of 180 mV for modulation depths of 55-100 % with 40-160 kb/s data rates. A total power consumption of less than 290 nW is achieved at a 1.2 V power supply. Effects of the input signal additive white noise as well as the process and temperature variations on the signal demodulation is also investigated in this paper. [ABSTRACT FROM AUTHOR]

Abstract: The development of low-voltage SRAM bitcells with ultra-low static power consumption has become a primary focus of memory design in recent years. The analysis of these bitcells requires the evaluation of dynamic noise margin metrics in addition to the traditional static noise margins. In this paper, we extend the presentation of our recently proposed quasi-static RAM (QSRAM) cell that employs an aggressive internal feedback technique for leakage suppression. In addition to the presentation of the QSRAM circuit topology and operation, a broad stability analysis of the cell is introduced, proving the functionality and bi-stability of the bitcell. Many of the recently proposed dynamic stability metrics used in this analysis have been demonstrated on standard SRAM bitcells; however, this is one of the first times these metrics have been used to analyze the functionality of an alternative implementation. Functionality of the proposed bitcell is shown for a sub-threshold 400mV supply voltage, providing a typical leakage reduction of 21X–45X as compared to a standard two-port bitcell operating at its nominal voltage. An 8kb QSRAM array was implemented and fabricated in a commercial low-power 40nm process demonstrating full functionality and ultra-low power consumption under a sub-threshold 400mV supply. [Copyright &y& Elsevier]

An ultra-low-power low-voltage 401-406 MHz Medical Device Radiocommunications Service (MedRadio) receiver for continuous wireless communication in biomedical applications is demonstrated using 0.18-μm CMOS technology. Although using a low-IF architecture, careful consideration is done for individual block-level circuit design to minimize the overall power consumption. The receiver chain consists of a complementary current-reuse LNA, an in-phase/quadrature folded mixer, an eighth-order complex bandpass filter, a limiting amplifier chain with RSSI, and a frequency synthesizer with a quadrature VCO. The proposed receiver achieves a gain of over 80 dB, noise figure of 14 dB, image rejection of 32 dB, and phase noise of −106 dBc/Hz at 100 kHz offset while consuming less than 1.2 mW from a 1-V supply voltage with 1.8 mm2 of core die area. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2821-2825, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27205 [ABSTRACT FROM AUTHOR]

Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 µm show a temperature coefficient of 16.9 ppm/°C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 µm². The lowest functional Vdd is 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC < 50 ppm/°C and \pm0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 µm, and 0.18 µm CMOS technologies. [ABSTRACT FROM AUTHOR]

An ultra-low-voltage ultra-low-power operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair. Two separate capacitors have been employed for the OTA compensation where one of them is used in a signal path and the other one in a non-signal path. The circuit is designed in the 0.18µm CMOS TSMC technology. The proposed design technique shows remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair OTAs. The Hspice simulation results show that the amplifier has a 92dB open-loop DC gain and a unity gain-bandwidth of 135 KHz while operating at 0.4V supply voltage. The total power consumption is as low as 386nW which makes it suitable for low-power bio- medical and bio-implantable applications. [ABSTRACT FROM AUTHOR]

Ultra Low power, High speed T flip-flop design is proposed in this paper. The design is based on Carbon Nanotube Field Effect Transistor (CNTFET) and is done in 32 nm technology. In order to increase the speed of flip-flop and to reduce the power dissipation CNTFET is used. CNTFET avoids most of the fundamental limitations of the traditional MOSFETs. This paper presents the performance analysis of CNTFET, structure, types of the new nano device, operation and various gate circuit design using CNTFET. This paper also presents the design and simulation of the T flip-flop. The results of the proposed design are compared with CMOS based T flip-flop. [ABSTRACT FROM AUTHOR]

Abstract: Demand of power efficient circuits has grown significantly due to fast growth of battery operated portable applications. Though, subthreshold operation of device shows huge potential towards satisfying the ULP requirement, it holds many challenging design issues. As integration density of interconnect increases at every technology node, increased delay and crosstalk become more challenging design issues particularly for subthreshold interconnects. Nanometer subthreshold interconnect faces subthreshold driver design challenges and problems due to increased interconnect capacitance. This paper explored the suitability of different conventional interconnects strategies and challenges to reduce the total path delay. It also proposed device and interconnect optimization techniques to achieve higher performance and to reduce crosstalk in future subthreshold global interconnects. The effect of variability on subthreshold interconnects have also been investigated. [Copyright &y& Elsevier]