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This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

A novel voltage comparator, termed an edge-race comparator (ERC), is proposed in this article. It compares the differential input voltage by generating two propagating edges in two inverter loops and by measuring the distance between the two edges. The two edges race with each other and the winner is finally determined. The comparator is low power and low noise and does not require high-voltage headroom. It can automatically adjust its noise, power consumption, and delay according to the input voltage, thereby saving significant energy and time in coarse comparisons and reducing the noise in fine comparisons (noise averaging is performed over a longer time in fine comparisons). It is well suited for low-power, high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) (SAR ADCs). Compared to a recently published edge-pursuit comparator (EPC), the proposed structure achieves 3.39 times faster speed at 1-mV input by using a novel configuration of two inverter loops with a distance measurement circuit. The energy consumption per comparison is reduced by 2.73 times at 1-mV input owing to the shorter required comparison time. Designed in a standard 40-nm CMOS process, the measurement results from an ADC show that the comparator energy at the LSB is reduced by 7.5 times, and the ADC sampling rate is increased by 3.85 times.

This brief presents an ultra-low-power (ULP) current reference circuit based on $V_{th}$ (threshold voltage), which consumes pico-watt of power under 0.5V supply voltage. Compared to traditional current references based on threshold voltage, this design uses no amplifier, thus friendly scaling and simple structure are achieved simultaneously. In order to save area, the huge resistor is replaced by a gate-leakage MOS transistor. The proposed circuit is designed in a 40nm CMOS process. The minimum supply voltage is 0.5V. Post simulation results show that the power consumption is only 8.2pW at 0.5V $V_{DD}$ at room temperature. According to our knowledge, this is the smallest power consumption compared to prior works, thanks to its simple structure. Under process + mismatch Monte-Carlo simulations, the temperature coefficient after trimming is 18.6ppm/°C over 0°C to 85°C. The core area is only 0.00025mm2 in layout. Apart from the 40nm process, this circuit is also designed in a 130nm process to demonstrate the robustness under different processes.