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Always-on keyword spotting (KWS) hardware is gaining popularity in ultra-low power IoT applications where specific words are used to wake up and activate the power hungry downstream system. This work proposes a low power KWS engine with a power-optimized Mel-frequency cepstral coefficients (MFCC) feature extraction module and a memoryoptimized long short term memory (LSTM) accelerator. Our LSTM model is pruned and compressed to reduce 89% of model size and 76% of computation. The LSTM accelerator adopts the weight stationary dataflow to reduce energy. Our simulation using a 40nm CMOS process achieves a power consumption of 2.51 μW, which is at least 2× lower than the state-of-the-art.

With the ability to generate different spiking patterns, Izhikevich model has well been considered a computationally efficient and biologically plausible neuron model for applications such as brain dynamic behavior study. This brief presents a low-cost, high-throughput digital hardware design for Izhikevich neuron model. The proposed design requires only addition, subtraction and logic shifts operations to achieve the low hardware cost. The dynamic behaviors of both the proposed neuron model and the original Izhikevich model were analyzed using the phase portraits. The FPGA implementation results demonstrated that the proposed design can reproduce different spiking patterns with very high throughput. Compared to existing designs, the proposed design achieves the lowest slices and LUTs utilization, which are 73% and 11% lower than the latest design (HOMIN), respectively.