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Your search keyword '"Sun, Wei-Tsun"' showing total 3 results
Start Over Author "Sun, Wei-Tsun" Topic [info.info-es]computer science [cs]/embedded systems
3 results on '"Sun, Wei-Tsun"'

1. Validating Static WCET Analysis: A Method and Its Application

Author

Sun, Wei-Tsun, Jenn, Eric, Cassé, Hugues, Centre National de la Recherche Scientifique - CNRS (FRANCE), Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Thales (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), IRT Saint Exupéry - Institut de Recherche Technologique (FRANCE), Institut de Recherche en Informatique de Toulouse - IRIT (Toulouse, France), IRT Saint Exupéry - Institut de Recherche Technologique, Thales (France), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Université Toulouse III - Paul Sabatier (UT3)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], nML, 000 Computer science, knowledge, general works, Architectures Matérielles, ISS, Validation of WCET tools, Computer Science, Système d'exploitation, Réseaux et télécommunications, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], Systèmes embarqués
Abstract

International audience; WCET analysis is a key activity in the development of safety critical real-time systems. Whether upper bounds on WCETs are obtained using static analysis or measurements, the confidence on the compliance of a system with its temporal requirements directly depends on the confidence on these estimations. Static WCET analysis based on abstract interpretation takes benefits from its formal foundations. However, it also strongly depends on the correctness of the underlying models. We hereby show how we have validated the version of the data flow static analyser of OTAWA applied to the AURIX TC275 target processor.

Published
2019
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2. Using execution graphs to model a prefetch and write buffers and its application to the Bostan MPPA

Author

Sun, Wei-Tsun, Cassé, Hugues, Rochange, Christine, Rihani, Hamza, Maiza, Claire, SUN, Wei-Tsun, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), VERIMAG (VERIMAG - IMAG), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
pipeline analysis, static analysis, VLIW, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Real-Time, WCET, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems
Abstract

International audience; Verifying the temporal properties of critical systems embedded in vehicles, like planes or cars, is crucial to avoid catastrophic issues. A key component of this verification is the Worst Case Execution Time (WCET) of the programs composing these systems. A common and sound approach to compute WCET is based on static analysis of the programs that requires, in turn, to precisely model the behavior and the timings of the hardware. Processor-specific features such as pipelines, caches, and buffers influence the hardware performances significantly. Hence taking processor features into account when estimating WCET is essential. Modeling the processor's features formally to ensure safe and accurate estimation is then a must. In this paper, we present the methodology applied to capture the behavior of prefetch and write buffers of the Kalray Bostan MPPA microprocessor, and to incorporate the established models with the Execution Graph (XG) to obtain WCET estimation. These analyses are then applied to the Mälardalen benchmark suite and the experimentation results validate the feasibility of our approach.

Published
2018

3. Dynamic Branch Resolution based on Combined Static Analyses

Author

Sun, Wei-Tsun, Cassé, Hugues, Institut National Polytechnique de Toulouse - INPT (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), and Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 000 Computer science, knowledge, general works, Dynamic branch, Assembly, Système d'exploitation, Réseaux et télécommunications, Static analysis, Systèmes embarqués, Machine language, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Architectures Matérielles, Computer Science, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], WCET
Abstract

International audience; Static analysis requires the full knowledge of the overall program structure. The structure of a program can be represented by a Control Flow Graph (CFG) where vertices are basic blocks (BB) and edges represent the control flow between the BB. To construct a full CFG, all the BB as well as all of their possible targets addresses must be found. In this paper, we present a method to resolve dynamic branches, that identifies the target addresses of BB created due to the switch-cases and calls on function pointers. We also implemented a slicing method to speed up the overall analysis which makes our approach applicable on large and realistic real-time programs.

Published
2016

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