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Due to the slow scaling of board and package technology, on-chip inductor has shown promising potential to enable more compact design and smaller parasitics for inductor-based designs, such as voltage regulator, resonant clocking, filter, etc. On the other hand, conventional on-chip 2D spiral inductor must be placed on the top metal layers, thereby consuming significant routing resources for global interconnects. Moreover, it may need more dedicated shielding to prevent unnecessary coupling, which further increases its occupied area. With the popularity of 2.5D and 3D chip architecture, Through-Silicon-Via (TSV) has been widely used, a significant portion of which are placed for thermal/manufacturability/reliability purposes. Thus, those redundant TSVs can be utilized to form the on-chip inductor for 2.5D/3D chips, with lower footprint and higher inductance density compared from the conventional spiral inductor. Unlike prior works focusing on the inductor itself, this paper discusses the optimization and application of such TSV-inductor from system perspective, including the optimization options and its design considerations. The possible design options including physical parameters, architecture and materials, to optimize the TSV-inductor are thoroughly investigated. Based on that, we further study a few key design scenarios to evaluate the design impact with use of such TSV-inductor and provide the design guidelines for its application in actual system designs.

The era of Big Data, Artificial Intelligence (AI) and Internet of Things (IoT) is approaching, but our underlying computing infrastructures are not sufficiently ready. The end of Moore’s law and process scaling as well as the memory wall associated with von Neumann architectures have throttled the rapid development of conventional architectures based on CMOS technology, and cross-layer efforts that involve the interactions from low-end devices to high-end applications have been prominently studied to overcome the aforementioned challenges. On one hand, various emerging devices, e.g., Ferroelectric FET, have been proposed to either sustain the scaling trends or enable novel circuit and architecture innovations. On the other hand, novel computing architectures/algorithms, e.g., computing-in-memory (CiM), have been proposed to address the challenges faced by conventional von Neumann architectures. Naturally, integrated approaches across the emerging devices and computing architectures/algorithms for data-intensive applications are of great interests. This paper uses the FeFET as a representative device, and discuss about the challenges, opportunities and contributions for the emerging trends of cross-layer co-design for CiM.

RRAM-based crossbars and optical neural networks are attractive platforms to accelerate neuromorphic computing. However, both accelerators suffer from hardware uncertainties such as process variations. These uncertainty issues left unaddressed, the inference accuracy of these computing platforms can degrade significantly. In this paper, a statistical training method where weights under process variations and noise are modeled as statistical random variables is presented. To incorporate these statistical weights into training, the computations in neural networks are modified accordingly. For optical neural networks, we modify the cost function during software training to reduce the effects of process variations and thermal imbalance. In addition, the residual effects of process variations are extracted and calibrated in hardware test, and thermal variations on devices are also compensated in advance. Simulation results demonstrate that the inference accuracy can be improved significantly under hardware uncertainties for both platforms.

At the era of big data, there have been growing demands for server memory capacity and performance. Memory network is a promising alternative to provide high bandwidth and low latency through distributed memory nodes connected by high speed interconnect. However, most of them implement the design from a pure-logic-level and ignore the physical impact from network interconnect latency, processor placement and the interplay between processor and memory. In this work, we propose a Physical-Aware framework for memory network design space exploration, which facilitates the design of an energy efficient and physical-aware memory network system. Experimental results on various workloads show that the proposed framework can help customize network topology with significant improvements on various design metrics when compared to the other commonly used topologies.

Content addressable memory (CAM) is widely used for data-centric computing for its massive parallelism and pattern matching capability. Though the CAM density has been improved by replacing the area-consuming SRAM with compact emerging nonvolatile memories (NVMs), its implementation has been limited to single level cell. To further boost the CAM density for data-intensive workloads, exploiting the multi-level cell NVMs is highly desirable. In this work, we demonstrate: 1) a novel scalable and ultra-compact multi-bit 2FeFET1T CAM design based on two ferroelectric FETs (FeFETs) and one transistor; 2) successful operations of the proposed CAM cell and array in experiment based on 2-bit FeFET memory, and sufficient sensing margin for an 1x32 CAM array through statistical analysis considering the device variation; 3) 22.6x area per bit saving compared with SRAM CAM; 4) 16x search speedup, and 29x reduction in energy delay product over the SRAM CAM approach in accelerating a database query processing application.

Optical neural networks (ONNs) have emerged as a promising high-performance computing platform to accelerate deep neural networks. In ONNs, phases of light are modulated through Mach-Zehnder Interferometers (MZIs), and MZIs are connected in a gridlike layout to implement multiply-accumulate operations. However, ONNs are very sensitive to process variations and thermal effects. This sensitivity leads to a significant degradation of inference accuracy of ONNs and thus renders them unusable in practice. In this paper, we propose a framework to calibrate process variations and counter thermal effects by power compensation. Experimental results demonstrate that the proposed framework can recover the inference accuracy under variations and thermal effects, e.g., from as low as 11.05% back to 74.11% for LeNet-5 on Cifar10, so that ONNs can achieve an inference accuracy similar to the accuracy after software training while providing their high bandwidth in neuromorphic computing.

The bottleneck between the limited memory bandwidth and high speed processing demands is the main cause of problems associated with high volume of data transfers in data-intensive applications. As a possible remedy to these issues, computing-in-memory (CiM) enables a subset of logic and arithmetic operations to be performed where the data resides, i.e., inside the memory. Various CiM designs have been proposed to date, based on different technologies. Given the variety of options available, picking the right design option for a system/application can be a complex task. When choosing a CiM design, it is important to establish evaluation conditions that are as uniform as possible to make a fair choice between available design options. In this paper, we describe a methodology for an uniform benchmarking of CiM designs. Our approach evaluates devices/circuits, arrays and the overall impact of CiM to a system with a framework based on Eva-CiM. As a case study, we analyze the array-level performance of 7 recent CiM designs implemented with SRAM, DRAM, FeFET-RAM, STT-MRAM, SOT-MRAM, and RRAM. After we identify that the FeFET-RAM-based design shows promising energy and delay savings at the array level, we carry out a system level evaluation showing that FeFET-RAM-based CiM outperforms a CMOS SRAM CiM baseline by an average of 60% across a set of 17 benchmarks (with respect to energy savings). Regarding speedups, both technologies offer virtually the same benefit of about 1.5X when compared to a situation where processing does not happen in memory.

It is a very important but difficult task to seek explicit variational formulations for nonlinear and complex models because variational principles are theoretical bases for many methods to solve or analyze the nonlinear problem. By designing skillfully the trial-Lagrange functional, different groups of variational principles are successfully constructed for two kinds of coupled nonlinear equations in shallow water, i.e., the Broer-Kaup equations and the (2+1)-dimensional dispersive long-wave equations, respectively. Both of them contain many kinds of soliton solutions, which are always symmetric or anti-symmetric in space. Subsequently, the obtained variational principles are proved to be correct by minimizing the functionals with the calculus of variations. The established variational principles are firstly discovered, which can help to study the symmetries and find conserved quantities for the equations considered, and might find lots of applications in numerical simulation.

Coal cities are an essential impetus for economic development and urbanization processes in China. However, a series of environmental issues provoked by resource exploitation cause the environmental sustainability of coal cities to face enormous challenges. Therefore, on the basis of the time series data of Yulin City from 1996 to 2017, this paper explores the nexus between socioeconomic development and industrial “three wastes” emissions by adopting the Tapio decoupling model, the environmental Kuznets curve (EKC) hypothesis, and the vector auto-regressive (VAR) model. The results show that Yulin’s economic development remains in an extensive stage and will not decouple from the environmental pollution in a short time. Except for the nexus of industrial solid waste and economic growth, which is an inverted U-shaped, the EKC hypothesis is not valid for industrial wastewater and industrial waste gas. Through the VAR (2) model, the impact of per capita gross domestic product (GDP) on industrial waste emissions is consistent with the results of the EKC hypothesis. Moreover, industrial waste emissions have a positive correlation with the per capita raw coal output, the energy consumption per unit of GDP, and the proportion of secondary industry. Hence, it is necessary to formulate targeted measures from industrial restructuring, industrial chain extension, governance model optimization, and waste comprehensive utilization to realize the environmental sustainability of coal cities.

Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other non-volatile memories (NVMs). Content Addressable Memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging nonvolatile memories (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domain simultaneously. By exploiting the multi-level-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit co-design of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS based CAM approaches, FeCAM is found to improve both memory density by 22.4X and energy saving by 8.6/3.2X for analog/digital modes, respectively. In the CAM-related application, our evaluations show that FeCAM can achieve 60.5X/23.1X saving in area/search energy compared with conventional CMOS based CAMs., 8 pages, 8 figures, accepted

Energy-harvesting internet-of-things devices must deal with unstable power input. Nonvolatile processors (NVPs) can offer an effective solution. Compact and low-energy arithmetic circuits that can efficiently switch between computation and backup operations are highly desirable for NVP design. This paper introduces a nonvolatile ferroelectric field-effect transistors (FeFET)-based sequential multiplier with the ability to do continued calculation after a power outage, thus achieving zero backup overhead. We exploit the unique characteristics of FeFETs to construct key components of a sequential multiplier. The multiplier relies on a FeFET-based adder and a new FeFET-based latch to achieve compact area and low operating energy. Moreover, it uses the hysteretic characteristic of FeFETs to realize the storage capability, and hence is able to store, at no extra cost, the intermediate data of an operation in a nonvolatile manner. This property provides support for continued computation when power supplies may be intermittent. Simulation results show that, assuming the same technology node, the proposed FeFET-based multiplier saves up to 21% and 19% area than a conventional CMOS-based sequential multiplier of 4-bits and 8-bits, respectively. It also saves 32% and 73% less area compared with a CMOS-based array multiplier. Furthermore, the proposed design can offer up to 32%/23% energy saving per operation compared with a 4/8-bit CMOS-based sequential multiplier.

Water environment monitoring is of great importance to human health, ecosystem sustainability, and water transport. Unlike traditional water quality monitoring problems, this paper focuses on visual perception of water environment. We first introduce the development of a customized aquatic sensor node equipped with an embedded camera sensor. Based on this platform, we present an efficient and holistic contamination detection approach, which can automatically adapt to the detection of floating debris in dynamic waters or the identification of salient regions in static waters. Our approach is specifically designed based on compressed sensing theory to give full consideration to the unique challenges in water environment and the resource constraints on sensor nodes. Both laboratory and field experiments demonstrate the proposed method can fast and accurately detect various types of water pollutants and is a better choice for camera sensor-based water environment monitoring compared with other methods.

This paper presents an L-2L de-embedding method for characterizing the electromagnetic properties of through-silicon-vias (TSVs) in 3-D ICs. To the best of our knowledge, this is the first paper that discusses the use of de-embedding method for multiport TSVs. The L-2L de-embedding structure and the analysis algorithm are first introduced. Then, the techniques for meeting two crucial requirements in accurately applying the method on multiport TSVs are proposed. To meet these two requirements, the de-embedding structure is designed to enhance the symmetry and the shielding TSVs are used to decrease the mutual admittance. The simulation results show that with the appropriate design, the shielding TSVs are able to greatly reduce the mutual admittance with little impact on TSVs and RDLs. Finally, the performance of the designed structures with and without shielding TSVs is examined via both full-wave simulation and the measurements. With the full-wave simulation results of TSVs as reference, it turns out that the de-embedding accuracy is significantly improved with the shielding TSVs. Moreover, the de-embedding results based on the measurements show good agreements with those of the simulation ones.

Pathology image segmentation is an essential step in early detection and diagnosis for various diseases. Due to its complex nature, precise segmentation is not a trivial task. Recently, deep learning has been proved as an effective option for pathology image processing. However, its efficiency is highly restricted by the inconsistent annotation quality. In this paper, we propose an accurate and noise-tolerant segmentation approach to overcome the aforementioned issues, which consists of a pre-processing module for data augmentation, a new neural network architecture, ANT-UNet, and a FCCRF inference module. Experimental results demonstrate that, even on a noisy dataset, the proposed approach can achieve more accurate segmentation with 4-23% accuracy improvement than other commonly used segmentation methods. Moreover, the proposed architecture is hardware-friendly and can be incorporated with a GPU acceleration flow to reach 24-128× speed-up.

This paper extends the [Formula: see text]-dimensional Broer–Kaup equations in continuum mechanics to its fractional partner, which can model a lot of nonlinear waves in fractal porous media. Its derivation is demonstrated in detail by applying He’s fractional derivative. Using the semi-inverse method, two variational principles are established for the nonlinear coupled equations, which up to now are not discovered. The variational formulations can help to study the symmetries and find conserved quantities in the fractal space. The obtained variational principles are proved correct by minimizing the functionals with the calculus of variations, and might find potential applications in numerical simulation. The procedure reveals that the semi-inverse method is highly efficient and powerful, and can be generalized to other nonlinear evolution equations with fractal derivatives.

Conventional on-chip spiral inductor consumes significant top metal routing area, thereby preventing its popularity in many on-chip applications. Recently TSV-inductor with a magnetic core has been proved to be a viable option for on-chip DC-DC converter in a 14nm test chip. The operating conditions of such inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, due to its unique TSV-structure, unlike conventional spiral inductor, much of the modeling details remain unclear. This paper analyzes the modeling details of a magnetic core TSV-inductor and proposes a design methodology to optimize power losses of the inductor. With this methodology, designers can ensure fast and reliable inductor optimization for on-chip applications. Experimental results show that the optimized magnetic core TSV-inductor can achieve inductance density improvement of 6.0--7.7X and quality factor improvements of 1.3--1.6X while maintaining the same footprint.

With increasing performance mismatch between processor and memory, "memory wall" has become the bottleneck of the entire computing system. In order to bridge the gap, processing-in-memory (PIM) has been revisited as a viable option to overcome the challenge, with various researches from devices to system. In this paper we present a complete design framework for PIM based acceleration with energy efficiency and performance improvement. The framework covers system level design and prototype architecture and software stack support to enable hardware accelerator design and optimization. It is also featured with configurability, easy access and effective evaluating and profiling. In the experiments, we analyzed a convolutional neural network to identify the least energy-efficient operation and replaced that by PIM acceleration. The experimental results show that the proposed accelerator is able to achieve up 6-9X performance gain for matrix multiplication as well as 10-15X energy improvement compared to conventional CPU-only implementation.

At sub-22nm regime, chip designs have to go through hundreds to thousands of steps and tasks before shipment. Many tasks are data and simulation intensive, thereby demanding significant amount of resources and time. Unlike conventional methodologies relying on experiences to manually handle data and extract models, recent advances in machine learning techniques enable the successful applications in various complex tasks to accelerate modern chip designs, ranging from pre-silicon verification to post-silicon validation and tuning. The goals are to reduce the amount of time and efforts to process and understand data through automatic and effective learning and enhancing from examples. In this paper we review and discuss several application cases of machine learning techniques, including pre-silicon hotspot detection through classification, post-silicon variation extraction and bug localization through inference, and post-silicon timing tuning through iterative learning and optimization, so as to leverage the potentials and inspire more future innovations.

This paper introduces CN-SIM, a cycle accurate, full system, power delivery (PD) noise simulator. CN-SIM provides a cross layer connectivity form application layer, to the architecture layer, to the circuit layer, which is much needed to realistically estimate PD noise. Thus, making it easier for system architects to explore multilayer design optimizations. CN-SIM's granularity at its deepest is at the functional unit (FU) level. The experimental results of running PARSEC suite benchmarks for different system configurations and different industrial PD design have illustrated CN-SIM's capability to capture the crosslayer impact on PD noise.

With continuously growing integration density and decreasing feature size, chip reliability, especially oxide breakdown (OBD) reliability is a concerning topic for chip designers. In the past, architects have to assume either worst case workload or maximum supply level to assess chip OBD reliability, which is easily pessimistic and induces unnecessary back-tracking in the design flow. In this paper, we present a cross-layer framework to enable more accurate OBD reliability assessment under actual workload and actual supply noise. The framework is capable of incorporating models at different design layers from architecture to circuit as a whole for fast and real-time reliability simulation. The experimental results show that the proposed framework can capture the actual degradation trend w.r.t. workload and supply level, and help reduce up to 90%design pessimism on lifetime estimation.

With the reduced noise margin brought by relentless technology scaling, power integrity assurance has become more challenging than ever. On the other hand, traditional design methodologies typically focus on a single design layer without much cross-layer interaction, potentially introducing unnecessary guard-band and wasting significant design resources. Both issues imperatively call for a cross-layer framework for the co-exploration of power delivery (PD) and system architecture, especially at early design stage with larger design freedom. Unfortunately, such a framework does not exist yet in the literature. As a step forward, this paper provides a run-time simulation framework of both PD and architecture and captures their interactions. Enabled by the proposed recursive run-time PD model, it handles an entire PD system on-the-fly simulation with

The goal of this work is to introduce and discuss different kinds of emerging technologies for logic circuitry and memory with respect to the key question of how they will impact future system-on-chip architectures and system-level management techniques. It is obvious that emerging technologies should have an impact there in order to fully exploit their technological advantages but also in order to deal with any disadvantages they might come with. In this special session paper, three promising emerging technologies are presented: (i) Negative Capacitance Field-Effect Transistor (NCFET) as a new CMOS technology with advantages primarily for low-power design, (ii) Ferroelectric FET (FeFET) as a non-volatile, area-efficient and low-power combined logic and memory as well as (iii) a Phase-Change Memory (PCM) and Resistive RAM (ReRAM) offering a large potential for tackling the memory wall problem in the von Neumann architecture. Our analysis demonstrates that not only new computing paradigms are promoted by these new technologies, it will also be seen that the trade-offs between the classical design parameters of low power, performance etc. will shift and hence emerging technologies will offer new Pareto points in the design space of future on-chip architectures. In that context, this work is unique as it bridges the gap between the technology side and system/architecture-level side to draw a vision of new technologies and their impact on architectures and system-level management.