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The manipulation of fast domain wall motion in magnetic nanostructures could form the basis of novel magnetic memory and logic devices. However, current approaches for reading and writing domain walls require external magnetic fields, or are based on conventional magnetic tunnel junctions (MTJs) that are not compatible with high-speed domain wall motion. Here we report domain wall devices based on perpendicular MTJs that offer electrical read and write, and fast domain wall motion via spin-orbit torque. The devices have a hybrid free layer design that consists of platinum/cobalt (Pt/Co) or a synthetic antiferromagnet (Pt/Co/Ru/Co) into the free layer of conventional MTJs. We show that our devices can achieve good tunnelling magnetoresistance readout and efficient spin-transfer torque writing that is comparable to current magnetic random-access memory technology, as well as domain wall depinning efficiency that is similar to stand-alone materials. We also show that a domain wall conduit based on a synthetic antiferromagnet offers the potential for reliable domain wall motion and faster write speed compared with a device based on Pt/Co. Domain wall devices based on perpendicular magnetic tunnel junctions with a hybrid free layer design can offer electrical read and write, and fast domain wall motion driven via spin-orbit torque.

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show the directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300-mm CMOS fab on full wafers, which clears the path for large-scale integration. This proof of concept, thus, offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications.

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300 mm CMOS fab on full wafers which clears the path for large scale integration. This proof-of-concept thus offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications.

Novel mask absorber designs are calling attention of the EUVL community due to their ability to mitigate mask 3D effects. Material selection is part of such optimization [1]. In this paper we propose several candidates as novel EUV lithography mask absorbers, namely TaTeN, Ru-Ta and Pt-Mo alloys. The choice of these materials is based on their theoretical performance evaluated by EUV imaging simulation based on their complex refractive index N(λ) = n(λ) +ik(λ), where the optical constants n and k relate to the phase velocity and to the absorption of an electromagnetic radiation with a wavelength λ, respectively. The materials are deposited as thin films on Si substrate with an additional Ru layer to mimic the cap of multilayer mirror (MLM) on the real mask. The experimental n and k values are determined by analyzing EUV reflectivity data obtained using a 13.5 nm synchrotron EUV radiation. The imaging simulation presented in this paper consists of calculation of several imaging metrics like non-telecentricity, normalized image log-slop (NILS), and threshold-to-size for specific use cases using the novel absorber. It also compares the proposed materials to the reference TaBN absorber. TaTeN shows higher absorption than TaBN and refraction closer to 1, which improves phase matching for a high k absorber. The refractive index of Ru-Ta and Pt-Mo alloys exhibits a large difference to that of air and provides the required phased shift of attenuated phase shift masks [2]. The characterizations of these materials target the requirements of an EUVL mask: durability for mask cleaning, mask lifetime and etchablity for mask patterning. The stability is first tested against several standard mask cleaning solutions by beaker test up to 24 hours with the film structure monitored by X-ray reflectivity analysis. The samples are also exposed to hydrogen plasma to imitate the working environment in a EUV scanner. Material integrity is checked with Rutherford backscattering spectroscopy before and after the exposure. Concerning material patterning, chemical reactive ion etch is applied for preliminary tests. A proper etch recipe is found for TaTeN with good etch rate (about 60 nm/min) and good selectivity to Ru underlayer (Ru etch is ignorable).

We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOS-compatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development., Presented at VLSI 2019 Circuit and Technology Symposium, JFS4p5

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400 °C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 A without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 A CoFeB polarizer from 125% to 145% for a similar RA product after a 300 °C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 A CoFeBTa reference layer spacer can even withstand annealing at 400 °C for 90 min and can retain a TMR value of 100% at RA 10 $\Omega \cdot \mu \text{m}^{2}$ , while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer.

Low write error rate (WER) is an important requirement for spin-transfer torque magnetic random access memory to be developed as a product. However, there have been reports about back-hopping phenomena that disturb achieving low WER. We demonstrate the experimental observation of back-hopping from the behavior of the WER in perpendicular magnetic tunnel junctions. WER decreases as pulse voltage (Vp) increases, but increases back as Vp increases further. It is attributed to the back-hopping, which originates from flipping of the reference layer (RL) and consequent alternating reversal of RL and free layer. Thus, it is necessary for the RL to be more stable and robust to avoid the back-hopping and to achieve low WER. We performed switching experiments on the devices of different stacks, which reveal back-hopping was the most severe in a magnetic tunnel junction device with the weakest coupling strength of the RL, and was significantly suppressed with a strongly coupled RL.

At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 103 at 63-percentile, to even 107 when applying percentile scaling to 1 ppm.

We present a scaled device based on magnetic domain wall (DW) transport for logic applications. The device consists of multiple magnetic tunnel junctions (MTJs) connected by the same magnetic free layer (FL). Magnetic domain walls are injected by spin-transfer torque (STT) at the input MTJs and are sensed by tunneling magnetoresistance (TMR) at the output MTJ after propagation through the FL. Logic functions can be built by merging several domain walls. By enabling real-time detection of long range DW transport, we demonstrate a spintronic component which can be used for either Boolean or non-Boolean logic.

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ., presented at VLSI2018 session C8-2

For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications. Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pinning layer and control diffusion, which enables BEOL compatibility while keeping TMR as high as 184%. In addition, we demonstrate that using such synthetic ferro-magnetic stack (SFM) design with TICPB layer allows a free layer off-set control and a switching current of 3.8 MA/cm2 in 25 nm e-CD devices.

The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including etch techniques (ion beam etch and reactive ion etch), post etch treatments and variations of the spacer layers in the MRAM stack. We find that variability in breakdown characteristics can be significantly reduced using an optimized etch. Secondly we propose an oxygen scavenging model to explain the different reliability behavior for various stack configurations.

Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall (DW) motion. In particular, it is a significant step toward the realization of a majority gate, even though further downscaling may be required. To our knowledge, this is the first fabrication of a cross-shaped free layer shared by several perpendicular MTJs. The fabrication process can be generalized to any geometry and any number of MTJs. Thus, this framework can be applied to other spin logic concepts based on magnetic interconnect. Moreover, it allows exploration of spin dynamics for logic applications, Comment: submitted to Japanese Journal of Applied Physics

© 2018 Author(s). Analogous device parameters in both the parallel (P) and anti-parallel (AP) states ensure a symmetric spin-transfer-torque magnetic random-access memory operation scheme. In this study, however, we observe an increasing asymmetry in the performance metrics with operating temperature of the bottom-pinned perpendicular magnetic tunnel junction (p-MTJ) devices. A temperature-dependent increase in the contribution of the stray field is observed in the tunneling magnetoresistance loop analysis. The switching current for P-to-AP decreases by 30% in the thermally activated switching regime by increasing the temperature from 300 K to 400 K, while it remains similar for AP-to-P. In addition, with the same temperature range, the thermal stability factor for the P state decreases 20% more than that for the AP state. We attribute those observations to the increase in the overcompensation of the stray field from the synthetic anti-ferromagnet structure. Saturation magnetization (M S ) of the [Co/Pt] x -based multilayers is much less affected by temperature [M S (400 K)/M S (300 K) = 97%] compared to that of the CoFeB-based multilayers (88%). Such an impact can be more severe during the electrical switching process due to the Joule heating effect. These results suggest that, to understand and to evaluate the performance in a wide range of temperatures, it is crucial to consider the contribution of the entire magnetic components in the p-MTJ stack. ispartof: APPLIED PHYSICS LETTERS vol:113 issue:14 status: published

With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free layer and its propagation towards the output pillar sensed by tunneling magneto-resistance. Domain pinning conditions are studied quasi-statically showing a strong dependence on pillar size, ferromagnetic free layer width and inter-pillar distance. Addressing pinning conditions are detrimental for cascading and fan-out of domain walls across nodes, enabling the realization of domain-wall-based logic technology.

Over the recent years, extreme ultraviolet (EUV) lithography has demonstrated the patterning of ever-shrinking feature sizes (enabling the N7 technology node and below), whereas the EUV mask has remained unaltered, using a 70-nm tantalum (Ta)-based absorber. This has led to experimentally observed mask three-dimensional (M3D) effects at the wafer level, which are induced by the interaction between the oblique incident EUV light and the patterned absorber with typical thickness values on the order of several wavelengths. We exploit the optical properties of the absorber material of the EUV mask as an M3D mitigation strategy. Using rigorous lithographic simulations, we screen potential single-element absorber materials for their optical properties and optimal thickness for minimum best focus variation through pitch at the wafer level. In addition, the M3D mitigation by absorber material is evaluated by process window comparison of foundry N5-specific logic clips. To valid ate the rigorous simulation predictions and test the processing feasibility of the alternative absorber materials, we have selected the candidate single elements nickel and cobalt for an experimental evaluation on wafer substrates. We present the film characterization as well as the first patterning tests of these single-element candidate absorber materials.

Thin SiGe-on-insulator (SGOI) substrates with Ge content varying between 42 and 93% were produced by the Ge condensation technique and full structural characterization was carried out. In a second step, the electrical properties of these substrates were analyzed by the pseudo metal-oxide semiconductor field-effect transistor technique which allowed determination of the carrier low-field mobilities, as well as the density of fixed charges in the buried oxide (BOX) and the density of interface traps at the BOX-SiGe film interface. Optimization of intermediate anneals in argon during the condensation process made the production of high crystalline quality and high-mobility substrates possible (up to 400 cm 2 V -1 s -1 for a 93% SGOI). Opposite trends were observed for holes and electrons: while the hole mobility increases with increasing Ge content, the electron mobility decreases. In addition, the density of interface traps and also the density of oxide charges were found to increase with increasing Ge content. Possible causes for this increase are discussed.

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm2 after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

Over the recent years EUV lithography has demonstrated the patterning of ever shrinking feature sizes (enabling the N7 technology node and below), while the EUV mask has remained unaltered using a 70nm Ta-based absorber. This has led to experimentally observed Mask 3D (M3D) effects at wafer level, which are induced by the interaction between the oblique incident EUV light and the patterned absorber with typical thickness values in the order of several wavelengths. In this paper we exploit the optical properties of the absorber material of the EUV mask as M3D mitigation strategy. Using rigorous lithographic simulations, we screen potential single element absorber materials for their optical properties and their optimal thickness for minimum best focus variation through pitch at wafer level. In addition, the M3D mitigation by absorber material is evaluated by process window comparison of foundry N5 specific logic clips. In order to validate the rigorous simulation predictions and to test the processing feasibility of the alternative absorber materials, we have selected the candidate single elements Nickel and Cobalt for an experimental evaluation on wafer substrates. In this work, we present the film characterization as well as first patterning tests of these single element candidate absorber materials.