Search

Comprehensive review and reanalysis are done on previously reported experimental hot carrier degradation data in various MOSFET architectures. The universality of time kinetics and voltage acceleration of degradation, obtained using multiple measurement techniques, is analyzed for OFF- and different ON-state modes in long and short channel planar and drain extended MOSFETs and FinFETs. The similarities and differences of such diverse measurement methods are analyzed. Existing theories are qualitatively benchmarked against this analysis, and capabilities as well as inconsistencies of those theories are discussed.

In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple- carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.