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In this article, an optimized carbon-doped AlGaN/AlN super-lattice (SL) buffer structure for GaN-based high electron mobility transistors, grown on 200-mm Si wafers is demonstrated. The resulting transistor structure features: 1) maximum vertical breakdown strength as high as 2.72 MV/cm, 2) vertical breakdown voltages (BVs) above 1.2 kV, 3) lateral BVs above 2.2 kV, 4) reduction in buffer traps, which is expected to result in low-dynamic $R_{ \mathrm{\scriptscriptstyle ON}}$ , and 5) more than 50 years of extrapolated lifetime at 150 °C under 650-V bias. These were achieved by optimizing growth parameters by systematically varying the SL growth temperature, SL carbon-doping, ammonia flow, and SL pair count with adjusting the total buffer thickness. The detailed analysis shows fundamental improvements compared to a conventional carbon-doped (Al)GaN staircase buffer with the same thickness and comparable growth time.

In this article, the gate current in AlGaN/GaN high-electron mobility transistors is modeled in a surface potential-based compact model. The thermionic emission, the Poole–Frenkel emission, and the Fowler–Nordheim tunneling are the dominant mechanisms for the gate current in the forward- and reverse-bias regions. These conduction mechanisms are modeled within the framework of the ASM-GaN compact model, which is a physics-based industry-standard model for GaN HEMTs, hence yielding a consistent model for the drain and gate currents. The proposed model captures the gate voltage, drain voltage, temperature, and gate-length dependencies of the gate current. The results of dc gate-leakage measurements of two GaN HEMT, differing only in terms of gate length, over a wide range of temperature, showing these current-conduction mechanisms, are presented, and the proposed model is validated accordingly. The developed gate current model, implemented in Verilog-A, is in excellent agreement with the experimental data.

In this paper, the advantages of GaN high electron mobility transistors (HEMTs) grown on native GaN over GaN/Si or GaN/sapphire substrates are investigated and correlated with epitaxial material quality. Transmission electron microscopy plan-view and cross-sectional analyses of GaN/GaN reveal dislocation densities below ${1} \times {10}^{{6}}$ cm−2, which is at least three orders of magnitude lower than that of GaN/Si or GaN/sapphire. In the case of GaN/Si, the dislocations not only originate from the substrate/nucleation layer interface, but also the strain relief and isolation buffer stacks are main contributors to the dislocation density. GaN/GaN HEMTs show superior electrical and thermal performance and feature three orders of magnitude lower OFF-state leakage. The current collapse (also referred to as current dispersion or $R_{ \mathrm{\scriptscriptstyle ON}}$ -increase) after stress bias is less than 15% compared with 50% in the case of GaN/Si. A 2% drop of the ON-state current due to self-heating in dc operation when compared with 13% and 16% for GaN/Si and GaN/sapphire, respectively. The GaN/Si thermal performance becomes comparable to that of GaN/GaN only after substrate removal. Therefore, GaN/GaN provides high ON-state current, low OFF-state leakage current, minimal current collapse, and enhanced thermal power dissipation capability at the same time, which can directly be correlated with the absence of high dislocation density.

Using an experimental AlGaN/GaN HEMT with a primary Schottky gate and three secondary MIS gates the charge trapping in the passivation layer and at the AlGaN/passivation interface layer is analyzed. The primary device is subjected to off-state drain-source voltage stress. This is followed by electrical characterization using the individual secondary gates, which allows for profiling the spatial distribution of trapped charges below the secondary gates and indicates less pronounced charge trapping towards the drain of the transistor. Experimental findings are verified by TCAD simulations. A physical equivalent network of the carrier injection and surface related trapping is proposed and experimentally verified. These novel results can be exploited for optimum field plate designs and improved compact models of HEMTs.

In this work we demonstrate a semi-empirical GaN HEMT model implemented in Verilog-A format. The model captures accurately the DC operation of test devices fabricated and measured at IMS CHIPS including the thermal effects. In addition, the off-state leakage current is physically modeled as a space-charge limited current prior to the onset of the physical breakdown. The dynamic current recovery of the transistor after stress bias is physically included by implementing the model in the form of a finite state machine, capturing the memory effect of the device. The drain current is modified to be a summation of multiple exponential terms, each corresponding to a given trapping center. This model can be used to predict the overall performance of the GaN HEMTs based on the epitaxial material composition or to infer the material composition and quality based on the measured device characteristics.