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Currently, commercial semiconductor-based memories face the problem of static energy consumption caused by leakage currents. Magnetoelectric random access memory (MeRAM), as a type of nonvolatile memory, provides a solution to this problem and can be used to replace the entire memory hierarchy as a universal memory. In contrast to spin transfer torque RAM (STT-RAM), MeRAM uses voltage controlled magnetic anisotropy (VCMA) effect to manipulate the switching of magnetic tunnel junctions (MTJs). MeRAM or VCMA-MTJ technology is more energy efficient and less likely to break down than STT-RAM. However, VCMA-MTJ suffers from serious write problems caused by variations in the VCMA coefficient, the external in-plane magnetic field, and the CMOS process. In this paper, a compact and SPICE-compatible VCMA-MTJ model is proposed. Then, a self-adaptive write circuit is proposed in which the write process is robust to variations in the VCMA coefficient and the external in-plane magnetic field. Finally, two practical methods are proposed to make our proposed self-adaptive write circuit also robust to 3 $\sigma$ CMOS process variations, as demonstrated by Monte Carlo simulations. The proposed self-adaptive write circuit can assist in the design of next-generation high-speed, low-power MeRAM chips.

Since Internet of Things devices should ideally be self-powered, there is great demand for devices with ultra-low operating voltages that can run on energy harvested from a noisy environment. In this paper, a novel all spin logic (ASL) device with voltage controlled magnetic anisotropy (VCMA) effect amplified by negative capacitance (NC) is proposed for the first time. This novel device can operate at a working voltage as low as 1 mV. A three-step pulse scheme is also proposed. Based on simulations of the VCMA effect and the NC effect coupled with the spin modular approach, the feasibility of the proposed ASL device with a 1-mV working voltage and its immunity to variations in device parameters and supply voltage are analyzed.

The high current density required by magnetic tunneling junction (MTJ) switching driven by the spin transfer torque (STT) effect leads to large power consumption and severe reliability issues, hindering the timetable for STT magnetic random access memory to mass market. By utilizing the voltage-controlled magnetic anisotropy (VCMA) effect, the MTJ can be switched by the voltage effect and is postulated to achieve ultralow power (fJ). However, the VCMA coefficient measured in experiments cannot meet the requirement for MTJ with dimensions below 100 nm. And an external in-plane magnetic field usually is demanded for precessional VCMA switching. Here, in this paper, a novel approach for the amplification of the VCMA effect, which borrows ideas from negative capacitance, is proposed. The feasibility of the proposal is proved by physical simulation and in-depth analysis. Since the amplified VCMA effect, the external magnetic field can be eliminated. A three-terminal novel MTJ memory cell is designed with which both low power and high speed can be achieved.

The making use of 2-D material as transistor channel is a rapid growth field since it can provide enough gate controllability for transistors at scaling limit. Among all kinds of 2-D materials, monolayer MoS2 stands out because of its large intrinsic bandgap and moderate mobility at room temperature. Most of the simulation work assumes the source/drain contacts of monolayer MoS2 transistors are Ohmic type, while in experiment the Schottky barrier contacts are more frequently seen. In this paper, the performance of single layer MoS2 double gate transistors with Schottky barrier contacts is evaluated with nonequilibrium Green’s function method. The image force lowering effect, which is crucial for accurate simulation of Schottky barrier, is taken into account. The simulation results reveal that increasing doping concentration is the most effective way to adjust monolayer MoS2 transistor performance. Transistor performance with Schottky barrier contacts can be comparable and even outperforms those with Ohmic contacts. The dependence of subthreshold swing, drain-induced barrier lowering and intrinsic delay on Schottky barrier height, source/drain extension length, and doping concentration in source/drain extension region are also simulated and analyzed. The effect of phonon scattering on performance of monolayer MoS2 transistor with Schottky barrier contacts and Ohmic contacts is also presented.

In this paper, we propose an all spin logic device with voltage controlled magnetic anisotropy (VCMA-ASL) and employ negative capacitance (NC) effect as a novel approach to amplify the VCMA effect. A new working strategy of 3-step operation scheme has been proposed, which reduces the energy consumption effectively as well as accelerates switching process.

In this work, novel magnetic memory device is proposed based on fascinating Spin Momentum Locking (SML) materials. The device utilizes direct spin current to charge current conversion and don't need Magnetic Tunneling Junction (MTJ) structure. The NOR, NAND and 3D array structure of the proposed magnetic memory device are demonstrated and discussed.