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A systematic post-deposition annealing study on Silicon Carbide (SiC) metal-oxide-semiconductor capacitors (MOSCAPs) using atomic layer deposition (ALD)-deposited silicon dioxide (SiO2) layers was carried out. Anneals were done in oxidising (N2O), inert (Ar) and reducing (H2:N2) ambients at elevated temperatures from 900°C to 1300°C for 1 hour. Electrical characterisation results show that the forming gas treatment at 1100°C reduces the flatband voltage to 0.23 V from 10 V for as-deposited SiO2 layers. The density of interface traps (DIT) was also reduced by one order of magnitude to 2×1011 cm-2 eV-1 at EC-ET = 0.2 eV. As an indicator of the improvement, characterisation by x-ray photoelectron spectroscopy (XPS) showed that silicon enrichment present in as-deposited layers was largely reduced by the forming gas anneal, improving the stoichiometry. Time-dependent dielectric breakdown (TDDB) results showed that the majority of forming gas annealed samples broke down at breakdown fields of 12.5 MV × cm-1, which is about 2.5 MV × cm-1 higher than for thermally oxidised samples.

This paper discusses the study of 4H Silicon Carbide (4H-SiC) Schottky rectifier structures based on the superjunction (SJ) principle. The effects of device geometry have been investigated to optimise the trade-off between breakdown voltage (VBD), specific on-resistance (RON,SP), and the ion-implantation fabrication window, so ensuring the final design is practically realisable. In this study, both full-SJ and semi-SJ (SSJ) layouts improve the VBD-RON,SP trade-off to below the 4H-SiC unipolar limit. In comparison to a conventional planar Schottky diode, full SJ structures, with p-pillars that traverse the full length of the n-drift region, have a 7x improvement in RON,SP for a 50-100 V reduction in VBD. In comparison, the SSJ structure is composed with the combination of the SJ structure and an n-bottom assist layer (BAL), which adds 2-μm of n-drift below the SJ pillars. The SSJ structure demonstrates a 5x improvement in RON,SP for a 300 V increase in VBD, for the same aspect ratio. Most favourably, the SSJ structure also has an ion-implantation processing window 60% higher than the full SJ device, offering better anti-charge-imbalance characteristics. In both full and semi layouts, a trench sidewall angled (α) at 80o was considered optimal, resulting in a slightly higher VBD and RON,SP, and a wider processing window, compared to vertical (90o) sidewalls.

This letter reports on initial investigation results on the material quality and device suitability of a homo-epitaxial 3C-SiC growth process. Atomic force microscopy surface investigations revealed root-mean square surface roughness levels of 163.21 nm, which was shown to be caused by pits (35 μm width and 450 nm depth) with a density of 1.09 × 105 cm−2 which had formed during material growth. On wider scan areas, the formation of these were seen to be caused by step bunching, revealing the need for further epitaxial process improvement. X-ray diffraction showed good average crystalline qualities with a full width of half-maximum of 160 arcseconds for the 3C-SiC (002) being lower than for the 3C-on-Si material (210 arcseconds). The analysis of C–V curves then revealed similar interface-trapped charge levels for freestanding 3C-SiC, 3C-SiC on Si and 4H-SiC, with forming gas post-deposition annealed freestanding 3C-SiC devices showing D IT levels of 3.3 × 1011 cm−2 eV−1 at E C−E T = 0.2 eV. The homo-epitaxially grown 3C-SiC material’s suitability for MOS applications could also be confirmed by leakage current measurements.

This letter reports on the improvement of a SiO2 layer formed by atomic layer deposition on 4H-SiC, using a post-deposition anneal in forming gas ambient. Capacitance–voltage measurements revealed good electrical properties, compared to a thermal oxide which was grown in N 2 O, with flatband voltage values averaging at -0.29 V and a low positive mobile ion charge density in the order of 1010 cm−2. XPS analysis revealed the FG annealed sample to have the most Si rich interface comparatively to other PDAs, with a C:Si ratio of 0.72, allowing more Si bonds to be terminated. SIMS analysis identified an increase in hydrogen near the interface of the FG-annealed sample with a peak concentration of 2.12 × 1021 cm−3. It is concluded that the improvement in electrical performance is due to the hydrogen passivating trap states at the SiO2/4H-SiC interface.