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In this article, heat generation distribution and maximum device temperature of gallium-nitride (GaN) high-electron-mobility transistors (HEMTs) are investigated by using the 2-D electrothermal and finite-element method (FEM) simulations. Devices with different gate lengths and source-to-drain spacing are investigated. It is observed that the maximum device temperature (TMAX) depends on the drain-to-source spacing and is almost independent of the gate length and that the assumption of a uniform heat generation region, under the gate, is not accurate; this is contrary to conventional calculation methods. Moreover, based on the results, a new approximation is proposed to use in the FEM simulations that can estimate TMAX more accurately. This method does not require physics-based technology computer-aided design (TCAD) simulations and can work with a low mesh density. The performance is compared with prior methods. This work was supported by Turkish Scientific and Technological Research Council, TUBITAK, under 1501 project GaNTURK. The work of Ekmel Özbay was supported in part by the Turkish Academy of Sciences.

In this work, highly linear AlGaN/GaN laterally gated (or buried gate) high-electron-mobility transistors (HEMTs) are reported. The effect of gate dimensions on source-access resistance and the linearity of laterally gated devices are investigated experimentally in detail for the first time. Transistors with different gate dimensions and conventional planar devices are fabricated using two-step electron beam lithography (EBL). Current–voltage, source-access resistance, small-signal, and two-tone measurements are performed to evaluate the linearity of devices. Contrary to conventional planar HEMTs, the intrinsic transconductance of laterally gated devices monotonically increases with increasing gate voltage, showing a similar behavior as junction field-effect transistors (FETs). The source-access resistance shows a polynomial increase with the drain current, which can be reduced by decreasing the filling ratio of the buried gates. Through the optimization of these two competing factors, i.e., intrinsic transconductance and the source-access resistance, flat transconductance with high linearity is achieved experimentally. The laterally gated structure shows flat transconductance and small-signal power gain over a larger span of gate voltage that is 2.5 times higher than a planar device. Moreover, 6.9-dB improvement in output intercept point (OIP3)/ ${P}_{\text {DC}}$ is achieved. This approach can be used to improve the linearity of AlGaN/GaN HEMTs at the device level.