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In view of the problems of low security, poor reliability, inability to backup automatically, and overreliance on the third party in traditional microgrid data disaster backup schemes based on cloud backup, the edge computing is used to preprocess power big data, and a microgrid data disaster backup scheme based on blockchain in edge computing environment is proposed in this paper. First, the honey encryption (HE) technology and advanced encryption standard (AES) are combined to propose a new encryption algorithm HE-AES, which is used to encrypt the preprocessed data. Second, the Kademlia algorithm is embedded in the edge server to realize the distributed storage and automatic recovery of microgrid data. Finally, the traditional proof of authority (PoA) consensus mechanism is improved partially, and the improved PoA is used to make each node reach consensus and pack blocks on the chain. The scheme can not only realize the data disaster backup automatically but also has high efficiency of data processing, which can provide a new idea for improving the current data disaster backup schemes.

The Internet of Things (IoT) becomes a leading field of computer science, which simplifies the life of human beings. The IoT, devices can interconnect and communicate with each other, in a fully autonomous mode. This autonomy has made the IoT network vulnerable to various security threats. However, due to this autonomy, there is a strong need for reliable security and storage mechanism for authentication to exchange data between IoT devices. To solve this problem, we propose an efficient method known as SCAB-IoTA, which ensures identification and authentication of IoT devices and also provides secure communication in the open environment. Along with authentication and secure communication, the scheme also ensures data integrity. SCAB-IoTA used the blockchain and hybrid cryptosystem (the combination of Advanced Encryption Standard (AES) and Elliptic Curve Digital Signature Algorithm (ECDSA) cryptographic techniques) to enhance the security of IoT applications to prevent various attacks along with less computational, and storage overhead. Furthermore, we have a secure cluster of IoT devices based on angular distance (AD), so that devices can securely communicate without any interruption. A secure and robust trust mechanism has employed to build these clusters, where each IoT device has to authenticate itself before joining the cluster. The obtained results satisfy the IoT security requirements with 60% reduced computation, storage and communication cost compared with state-of-the-art methods. The security analysis illustrates that SCAB-IoTA withstands against various cyberattacks such as impersonation, message replay, man-in-the-middle, and botnet attacks.

Persistent fault analysis (PFA) is a newly proposed cryptanalysis for block ciphers. Although the injected fault is persistent during the entire encryption, the corresponding analysis is only applied to the last round in the original PFA. In this article, the enhanced PFA (EPFA) is proposed, which can push the limit of PFA by exploiting the fault leakage in deeper rounds and target to reduce the number of required ciphertexts as small as possible. EPFA is first introduced as a general method with a specific application to advanced encryption standard (AES). Then it is extended to other substitution–permutation network (SPN)-based block ciphers, such as LED and SKINNY, both of which have unique features that EPFA fits well. To improve the efficiency of EPFA, a parallel algorithm based on mixed radix numbers is developed, which fully utilizes the power of GPU. Our experimental results show that EPFA can reduce the number of required ciphertexts to be under 1000, which is only about 40% of the 2500 ciphertexts in previous PFA on AES. In contrast to the single-threaded implementation, the parallel EPFA can have a speedup roughly about 200 times.

A transient fault-based collision attack always requires to inject fault multiple times. We present the first attack that uses collision information caused by a persistent fault in the substitution box (S-box) to recover the entire 128-bit key of the advanced encryption standard (AES). Moreover, a relatively relaxed fault model is required; i.e., the attacker does not know any information about the position, the length (i.e., the number of bytes), or the value of the injected fault. At most, 4096 chosen plaintexts are required for a persistent fault-based collision attack (PFCA), and the computational complexity is $O(2^{23})$ in the worst case in the single-byte fault setting. A filtering algorithm is presented in the multibyte fault setting, and we theoretically prove that the complexity can be reduced to $O(2^{12})$ in more than half of cases if the number of collision ciphertexts follows a uniform distribution. In addition, PFCAs against a software implementation of AES are simulated on a laptop, and the results show that the success probability of the attack either with online key searching or with offline key searching approaches 100%. In particular, more than 97% of all experiments output the right key with complexity $O(2^{12})$ in the multibyte fault setting. Therefore, the attack is more efficient in this scenario. Furthermore, the attack works on an AES implementation protected by Boolean masking. Finally, PFCAs against AES implementations separately protected by two widely used countermeasures—the inverse S-box and the parity-1 matrix—are performed. The experimental results illustrate that only a 10-round protection using the first method can completely defeat the attack.

We present a side-channel-attack (SCA) resistant asynchronous-logic (async-logic) Advanced Encryption Standard (AES) accelerator with dual-hiding SCA countermeasures, i.e. the amplitude moderation (vertical dimension) and the time moderation (horizontal dimension). There are five contributions in this paper. First, we propose an async-logic design flow with relative timing to simplify the AES realization in Field-Programmable-Gate-Array (FPGA). Second, we optimize completion detection circuits therein to achieve a low power/overhead solution. Third, we propose a randomized delay line control and a data-propagation control to amplify the dual-hiding SCA countermeasures for our async-logic AES accelerator. Fourth, we validate the async-logic design flow based on two commercially-available Sakura-X and Arty-A7 FPGA boards. Fifth, we comprehensively evaluate 74 SCA attacking models for our async-logic AES accelerator on these two boards, and compare the results against a benchmarking AES based on synchronous logic (sync-logic). We show that our async-logic AES accelerator is unbreakable within 1 million electromagnetic (EM) traces where the sync-logic counterpart is breakable within < 30K EM traces. To our best knowledge, our async-logic AES accelerator is the first async-logic AES design evaluated comprehensively at the first/last round, at various attacking locations (i.e. before/after Substitute-Box), and with various Hamming weight/distance, bit model, and zero-model of SCAs. National Research Foundation (NRF) Accepted version This research project is supported by the National Research Foundation, Singapore under its National Cybersecurity R&D (NCR) Research Programme in Assuring Hardware Security by Design in Systems on Chip, SOCure (NRF2018NCR-NCR002- 001), and NTUtive GAP fund (NGF-2017-03-013).

Cloud computing helps users to store and retrieve their data in the cloud online on an as-per-pay basis anytime, anywhere in the world. As a consequence, the security of data stored in the cloud serves as a key concern for cloud consumers due to ongoing hacking incidents in the cloud. Both cloud service providers (CSPs) and consumers face various attacks that pose a serious threat to both the organization and the user. Therefore, a robust intrusion detection system (IDS) needs to be configured to identify and avoid potential attacks in the cloud at an earlier stage. The state-of-the-art IDS system which used shallow machine learning techniques suffered from poor accuracy with a higher false alarm rate and higher response time. To overcome this problem, a hybrid semantic deep learning (HSDL) architecture is developed in this paper by integrating the long short-term memory (LSTM), convolutional neural network (CNN), and support vector machine (SVM) architectures. The semantic information present in the network traffic is identified using a semantic layer known as the Word2Vec embedding layer. The HSDL model classifies the intrusion present in the text along with its corresponding attack class. The normal text without any trace of intrusion is encrypted using an advanced encryption standard (AES) algorithm to enhance cloud storage security, and the optimal key with the largest key breaking time for the AES algorithm is selected using the crossover-based mine blast optimization algorithm (CMBA). The proposed HSDL scheme is evaluated and tested using two real-time intrusion detection benchmark datasets, namely NSL-KDD and UNSW-NB15. The proposed model achieves an accuracy of 99.98% for the NSL-KDD and 98.47% for the UNSW-NB15 dataset, respectively. The experimental and security analysis conducted proves the efficiency and robustness of the proposed scheme.

Mobile-edge computing (MEC) has emerged as a new computing paradigm with great potential to alleviate resource limitations attributed to mobile device users (MDUs) by offloading intensive computations to ubiquitous MEC server. However, most of the current offloading policies allow MDUs to transmit their tasks to the same connected small base stations (sBSs), which invariably increases latency and limits performance gain due to overload. Moreover, the security issue mitigating sensitive communication of information is not adequately addressed. Therefore, in this study, in addition to proposing a joint load balancing and computation offloading (CO) technique for MEC systems, we introduce a new security layer to circumvent potential security issues. First, a load balancing algorithm for efficient redistribution of MDUs among sBSs is proposed. In addition, a new advanced encryption standard (AES) cryptographic technique suffused with electrocardiogram (ECG) signal-based encryption and decryption key is presented as a security layer to safeguard the vulnerability of data during the transmission. Furthermore, an integrated model of load balancing, CO and security is formulated as a problem whose goal is to decrease the time and energy demands of the system. Detailed experimental results prove that our model with and without the additional security layers can save about 68.2% and 72.4% of system consumption compared to the local execution.

Wireless body area networks (WBAN) consist of various sensors to collect essential data signals to monitor blood pressure, heartbeat, blood sugar level, pulse, and body temperature. However, such dense sensor networks face serious issues due to interference which degrades the system throughput. Similarly, data security is another important factor to be considered in WBAN. Interference can be avoided by dividing the sensors into a group based on their operational characteristics and data security can be enhanced using suitable encryption modules. Recently, cloud-based WBAN has gained more attention, as concepts of cloud offer various advantages for efficient data management and security factors. Considering these issues in WBAN and the advantages of a cloud environment, this research work proposes an enhanced data security through Advanced Encryption Standard (AES) and efficient task flow scheduling using Genetic Algorithm (GA). The proposed model outperforms better in task scheduling which greatly reduces the interference and increases the system throughput. The proposed model is experimentally validated in terms of throughput, execution time, response time, and encryption time. Conventional models such as DES and 3DES are used to compare the outcomes of the proposed model to validate the superior performance, and the proposed model performs better than conventional models.

Data security is the focus of information security. As a primary method, file encryption is adopted for ensuring data security. Encryption algorithms created to meet the Data Encryption Standard (DES) and the Advanced Encryption Standard (AES) are widely used in a variety of systems. These algorithms are computationally highly complex, thus, the efficiency of encrypting or decrypting large files can be drastically reduced. To this end, we propose an optimized algorithm that efficiently encrypts and decrypts large files by parallelizing processing tasks on a single heterogeneous many-core processor in the Sunway TaihuLight computer system. Firstly, we convert the serial DES and AES programs to our experimental platform. Then we implement a task assignment strategy to test the converted algorithms. Finally, in order to optimize parallelized algorithms and improve data transmission performance, we apply the master-slave communication optimization, the three-stage parallel pipeline, and vectorization. Extensive experiments demonstrate that our optimized algorithm is faster than the state-of-the-art open-source implementations of DES and AES. Compared with the serial processing algorithms, our parallelized DES and AES perform nearly 40 times and 72 times faster, respectively. The work described in this paper leverages existing methods and provides a sound basis for the direction of future research in data encryption.

Much of the Internet's communication is encrypted, and its content is only accessible at two endpoints, a client and a server. However, any encryption requires a key that must be negotiated without being revealed to potential attackers. The so-called TLS (Transport Layer Security) handshake is often used for this task without obviating that many fundamental parameters of TLS connections are transmitted explicitly. Thus, third parties have access to metadata, including information about the endpoints, how the connection is used. On the other hand, QoS is considered the central part of the communication used to judge the deliverable quality through several parameters (latency, jitter ...). This document describes a secure approach and meets mainly the requirements of quality of service on a communication channel (free, loaded, congested ...), using the robustness and flexibility of the TLS protocol represented on the characteristics of existing encryption keys on its list of "ciphers suites." We focused more particularly on the AES key (Advanced Encryption Standard), including the different sizes (128,192,256), given its resistance to various classical attacks (differential, linear, ...) and its lightness compared to other protocols such as DES, 3DES ... This method is useful in continuous communications in a time axis (video sequence, VOIP call...).

A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While previously reported linear low-dropout regulators (LDOs) offer improvements in minimum-time-to-disclose (MTD) of extracted key bytes in the time domain, their transformations are less effective against frequency-domain attacks. This article describes a non-linear digital LDO (NL-DLDO) with control loop randomizations that bolster SCA resistance in the frequency domain. The NL-DLDO cascaded with an AES engine augmented with arithmetic countermeasures enables $>250\text{K}\times $ improvement in MTD, with no CPA/CEMA/DNN attacks detected after 1-B encryptions, with 8% power and 10% area overheads incurred by arithmetic techniques. The RSA-4K crypto-processor implements exponent magnitude and timing randomizations along with dynamic memory addressing to mitigate time- and frequency-domain attacks. The countermeasures enable $711\times $ suppression in means separation in current/EM magnitudes from 3.1 mV to $4.35~\mu \text{V}$ , reducing attacker’s accuracy to an ineffective random guess classification, while limiting area and performance overheads to < 0.05% and 3.25%, respectively.

Academic degrees are subject to corruptions, system flaws, forgeries, and imitations. In this paper we propose to develop a blockchain smart contract-based application using Ethereum Platform, to store, distribute and verify academic certificates. It constitutes a trusted, decentralized certificate’s management system that can offer a unified viewpoint for students, academic institutions, as well as for other potential stakeholders such as employers. The article describes the implementation of three main parts of our proposed solution that includes: verification application, university interface and accreditor interface. This application avoids administrative barriers, makes the process of deployment, verification, and validation of certificates faster, efficient, and more secure. Additionally, it offers confidentiality of the data by using AES encryption algorithm before creating transactions and allows bulk submission of multiple academic certificates.

The primary task of wireless sensor networks (WSNs) is to collect various types of data, for example, weather data, traffic data, etc. Collected data in WSNs are different from most data transmitted in digital communication applications. Most collected data in WSNs contain only few bits of information, but most data in data communication applications contain a large number of bits. All existing data encryptions in WSNs use conventional symmetric-key encryptions (e.g., advanced encryption standard (AES)) in which each large-size key is used to encrypt a block of large-size of data (e.g., a fixed block size of 128 bit in AES), and the security is based on a large-size of pairwise shared key (e.g., 128/192/ 256 bits in AES) between the sender node and the receiver node. Obviously, these conventional encryptions are not suitable for WSNs since the size of keys are much larger than the size of data. We propose a novel data encryption, in which it encrypts only few bits of data, and the security is based on multiple pairwise shared keys with short length. The encryption speed is much faster than conventional symmetric encryptions. Data aggregation is an efficient way to transmit data in a network. In the past, most encrypted data aggregations were designed based on public-key based homomorphic encryption. Public-key encryptions need time-consuming computation, so these schemes are not suitable for applications in WSNs. Most data in WSNs are routed through a path from the source node to the receiver node, which involves multiple sensor nodes. Our encrypted data aggregation is also called path-oriented data encryption. When multiple data are collected in WSNs, our scheme allows sensors in the path to aggregate all collected data in a piggyback ride. Our proposed encrypted data aggregation is a lightweight solution, which is suitable for applications in WSNs.

The sensing-as-a-service (SaaS) model has been explored to address the challenge of intractability of managing a large number of sensors faced by future smart cities. However, how to effectively share sensor data without compromising confidentiality, privacy protection, and fair trading without third parties is one of critical issues that must be solved in the SaaS in smart cities. While blockchain shows promise in solving these issues, the existing blockchain-based data sharing (BBDS) systems are difficult to apply to SaaS in smart cities because of many unresolved issues such as requiring a customized blockchain, huge storage, communication and computation costs, and dependence on a third party to achieve fair trading. We propose a BBDS system model with its security requirements before we present a concrete construction by combining -protocol, Paillier encryption scheme, and any secure symmetrical encryption and signature schemes. To demonstrate the utility of our proposed BBDS system, we present a security analysis and compare our system with other solutions. We implement the prototype in Remix to analyze the gas cost, and we conduct experiments to evaluate the communication and computation costs of the BBDS system using symmetric encryption (advanced encryption standard (AES)) and a signature scheme (elliptic curve digital signature algorithm (ECDSA)).

Currently, embedded systems can be found everywhere in quotidian life. In the development of embedded systems, information security is one of the important factors. Encryption is an efficient technique to protect information against attacks. However, because of constraints, existing encryption functions are not compatible and do not agree with real-time applications in embedded systems. In this paper, an improved cryptographic approach with a high level of security and high speed is put forward. Our work uses an efficient version of a hybrid scheme comprising an Advanced Encryption Standard (AES) - Elliptic Curve Cryptography (ECC) for medical image encryption, which combines the benefits of the symmetric AES to speed-up data encryption and asymmetric ECC in order to secure the interchange of a symmetric session key. The contribution of this paper consists of the following two main points: First, we put forward an optimized ECC hardware architecture to respect the compromise between area, power dissipation, and speed. Thus, we primarily utilize only two multipliers to develop the Point Addition (PA) block and the Point Doubling (PD) block, which reduces time complexity. Then, a 32-bit multiplier and a 32-bit inverter architecture based on shifts and XORs are proposed to reduce power consumption and area occupancy. Second, for image encryption, we primarily propose to modify the AES by eliminating the mix-columns transformation and replacing it with a permutation based on the shifts of columns, which decreases time complexity while maintaining the Shannon diffusion and the confusion principle. Then, an adjustment of the rearrangement of the general structure is given to enhance the entropy value. The global cryptosystem is implemented using a co-design approach where the modified AES runs on the NIOS II processor, and the scalar ECC multiplication is designed as a hardware accelerator. The suggested cryptographic system spends much less execution time, which is a significant factor for being applied in practice. Security analysis is successfully performed, and our experiments prove that our proposed technique provides the basics of cryptography with more simplicity and correctness. In fact, the results of the evaluation prove the effectiveness, rapidity and high security of the suggested algorithm.

The sensor networks have revolutionized wireless technology with next-generation internetworking and scalable infrastructure. Since, the autonomous sensor operates in vulnerable and unattended environmental conditions, hence, securing the sensed data becomes a critical issue. Advanced Encryption Standard popularly known as AES is one of the most common and extensively used algorithms for private key encryption in sensor networks. However, the substitution box lookup table is a time-consuming process in AES. Therefore, our research targets to improve the running time and throughput of AES by proposing a novel technique of splitting AES S-box followed with parallel substituting of two bytes at a time using multithreading. The proposed Enhanced-AES has the feasibility of implementation in the heterogeneous and hierarchical multicore sensor network. Energy consumption and execution time are the parameters used to evaluate the functioning of the Enhanced-AES. Our proposed model outperformed the existing security mechanisms; thereby increasing the lifetime of the sensor network and maintaining the data freshness.

The increasing complexity of the cryptographic modeling and security simulation of the Advanced Encryption Standard (AES) necessitate fast modeling and simulation security environment. The SystemC language is used in Electronic System Level (ESL) that allows cryptographic models to achieve high security and modeling simulation speed. Yet, the use of SystemC in the security simulation requires modifications of the original code which increases the modeling complexity. The Aspect-Oriented Programming (AOP) can be used in the cryptographic modeling and security simulations without any code modification. In this paper, a new AES SystemC model using the AOP technique is presented. A functional verification environment is proposed to test the functionality of the AES SystemC AOP model, the impact of AOP on simulation time, and the size of the executable files. The design of the AES model is developed with the weaving of all modules by AspectC++ which is an AOP language. The Simulation results show the efficiency of the proposed AES model and the uses of the AOP technique do not have a significant impact on simulation time or on the size of the executable file.

An evolutionary asymmetric cryptosystem is proposed using QWT + SPIHT and AES. This system is based on the Quincunx wavelet transform coupled with progressive encoder SPIHT (QWT + SPIHT) and encrypted by the algorithm “Advanced Encryption Standard” (AES). The numerical results demonstrate that the proposed system is feasible and effective for encryption. The characteristics of the proposed transmission system are as follows. First, the progressive SPIHT encoder performs partial encryption on the compressed image and hash of the image to obtain secure deduplication of the image. Second, the use of the AES encryption algorithm can greatly improve security, such as an attack without phase recovery and information disclosure. The proposed method effectively prevents information leakage. However, adopting a Quincunx wavelet transformation reduces the amount of data, which is more conducive to data transmission and increases the practicability of the system.

A modified XXTEA “M-XXTEA” symmetric block cipher that has a simple construction compared to the advanced encryption standard (AES) is proposed. It is efficient for protecting limited-resource devices such as IoT smart devices. The M-XXTEA will be able to achieve confidentiality during transmission of data over the internet. Since the original XXTEA was vulnerable against key-related and chosen-plaintext attacks. Therefore, this paper introduces a new and robust version of the original XXTEA by employing an improved S-box to enhance security to overcome such types of attacks. Besides, the M-XXTEA is coupled with a chaotic key generator system adding a layer of security achieving the idea behind the one-time pad. The cipher keys are dynamically changing for each block of plaintext when encrypted. Thus, it provides a more robust security mechanism than the original XXTEA and the AES. Besides enhancing data security, the M-XXTEA can function with different sizes of text blocks and with different key sizes. Several experiments are implemented to compare the performance of the M-XXTEA with the original XXTEA and with the AES. Results show that the M-XXTEA encryption and decryption time efficiencies outperform AES by 60%. Besides, the M-XXTEA achieves speed efficiency 57% better than the AES. It can be used efficiently for protecting IoT smart devices in the industry, and e-health systems, and smart cities.

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This paper presents a 3 in 1 standalone FPGA system which can perform color image blur detection in parallel with compression and encryption. Both blur detection and compression are based on the 3-level Haar wavelet transform, which is used as a common building block to save the resources. The compression is based on performing the hard thresholding scheme followed by the Run Length Encoding (RLE) technique. The encryption is based on the 128-bit Advanced Encryption Standard (AES), which is considered one of the most secure algorithms. Moreover, the modified Lorenz chaotic system is combined with the AES to perform the Cipher Block Chaining (CBC) mode. The proposed system is realized using HDL and implemented using Xilinx on XC5VLX50T FPGA. The system has utilized only 25% of the available slices. Furthermore, the system can achieve a throughput of 3.458 Gbps, which is suitable for real-time applications. To validate the compression performance, the system has been tested with all the standard $256\times 256$ images. It is shown that depending on the amount of details in the image, the system can achieve 30dB PSNR at compression ratios in the range of (0.08-0.38). The proposed system can be integrated with digital cameras to process the captured images on-the-fly prior to transmission or storage. Based on the application, the blurred images can be either marked for future enhancement or simply filtered out.

This paper presents UCloD, a novel random clock delay-based robust and scalable countermeasure against recently discovered remote power analysis (RPA) attacks. UCloD deploys very small clock delays (in the picosecond range) generated using the tapped delays lines (TDLs) to mitigate RPA attacks. UCloD provides the most robust countermeasures demonstrated thus far against RPA attacks. RPA attacks use delay sensors, such as Time to Digital Converters (TDC) or Ring Oscillators (ROs) to measure voltage fluctuations occurring in power delivery networks (PDNs) of Field Programmable Gate Arrays (FPGAs). These voltage fluctuations reveal secret information, such as secret keys of cryptographic circuits. The only countermeasure proposed thus far activates ROs to consume significant power and has managed to secure Advanced Encryption Standard (AES) circuits for up to 300,000 encryptions. Using TDLs available in FPGAs, UCloD randomly varies the clock to the cryptographic circuits under attack to induce noise in the adversary’s delay sensor(s). We demonstrate correlation power analysis (referred to as CPA) attack resistance of UCloD AES implementations for up to one million encryptions. Compared to an unprotected AES circuit, UCloD implementations have minimal overheads (0.2% Slice LUT overhead and 4.8% Slice register overhead for Xilinx implementations and 0.5% LogicCells overhead for Lattice Semiconductor implementations).

Fog computing complements cloud computing by removing several limitations, such as delays and network bandwidth. It emerged to support Internet of Things (IoT) applications wherein its computations and tasks are carried out at the network’s edge. Heterogeneous IoT devices interact with different users throughout a network. However, data security is a crucial concern for IoT, fog and cloud network ecosystems. Since the number of anonymous users increases and new identity disclosures occur within the IoTs, it is becoming challenging to grow mesh networks to deliver end to end communications, as the extended IoT networks resemble a mesh architecture. To reinforce data security over IoTs, we deploy a microservice-based blockchain mechanism for fogs, which works as a decentralized client-server network medium (i.e., secured end device-based communication). We implement a blockchain equipped security scheme to be used with a fog-IoT hierarchical tree-based overlay mesh architecture to address and develop the network performance issues. In this study, we consider encryption and decryption delays from IoT and fog-integrated parts to monitor data records and compare them through the developed security scheme. The blocks of a blockchain offer the desired execution results mainly in terms of the algorithmic efficiency, which correlates with the existing algorithms, namely the Advanced Encryption Standard (AES), the Rivest Shamir Adleman (RSA), and the Data Encryption Standard (DES). Our ‘BFIM’ scheme has an enhanced task scheduling capacity and a more efficient throughput than the AES, DES, RSA resource deliverables (i.e., tasks). Our comprehensive performance evaluation implies that the Blockchain-based Fog IoT Microservice (i.e., BFIM) architecture provides a task delivery efficiency of 78.79% (i.e., task deliverable) and a service delivery efficiency of 83.24% (i.e., task scheduling). The ‘BFIM’ also has an overall process delivery efficiency of 75% (i.e., time delay, throughput) in the fog layer, rather than a central cloud layer running the AES, DES, and RSA algorithms.

Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT), providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem based on the requirement of resource-constrained IoT devices. This article presents a lightweight advanced encryption standard (AES), a high-secure symmetric cryptography algorithm, implementation on field-programmable gate array (FPGA) and 65-nm technology for resource-constrained IoT devices. The proposed architecture includes 8-bit datapath and five main blocks. We design two specified register banks, Key-Register and State-Register, for storing the plain text, keys, and intermediate data. To reduce the area, Shift-Rows is embedded inside the State-Register. To adapt the Mix-Column to 8-bit datapath, we design an optimized 8-bit block for Mix-Columns with four internal registers, which accept 8-bit and send back 8-bit. Also, a shared optimized Sub-Bytes is employed for the key expansion phase and encryption phase. To optimize Sub-Bytes, we merge and simplify some parts of the Sub-Bytes. To reduce power consumption, we apply the clock gating technique to the design. Application-specific integrated circuit (ASIC) implementation results show a respective improvement in the area over the previous similar works from 35% to 2.4%. Based on the results, the proposed design is a suitable cryptosystem for tiny IoT devices.

To secure various forms of data, a polymorphic variant of the Advanced Encryption Standard (P-AES) has been introduced. In the P-AES, the AES parameters’ values will change with every new key. The exact values will be available only to legitimate communicating parties during execution time. To achieve these objectives, the basic AES transformations, SubBytes, ShiftRows, and MixColumns, have been made key-dependent in the proposed P-AES. Hence, with every new key, these transformations will operate differently. The receiver can retrieve the operations’ details from the encryption key. Consequently, polymorphism has been achieved and interoperability remains intact. P-AES has been implemented seamlessly using the existing AES modules, and the performance was more or less equal to the AES performance (71 and 70 milliseconds to encrypt 500 bytes using the P-AES and the AES respectively). From a security standpoint, the proposed P-AES fully complies with Kerckhoff’s principle. This means the cipher has an open design, and the security provided by the P-AES depends only on the secrecy of the encryption key. The cipher resistance to differential and linear attacks has been proved. Moreover, the resulting proposed cipher can operate in 128 different ways, which will significantly reduce the capabilities of any sophisticated attacker. Furthermore, the proposed P-AES’s scores of the key avalanche and the plaintext avalanche were 0.496 and 0.504 respectively. Finally, the Statistical Test Suite (STS) recommended by the NIST has been used to ensure the randomness of the cipher output, and the cipher has passed all the STS tests.

The prime aspect in data handling is the invulnerability of Data, therefore, Encryption is the most conventionally used technique for data security. for instance, Data Encryption Standard (DES), Rivest–Shamir-Adleman (RSA), Advanced Encryption Standard (AES) to attain it moreover, with the exponentially growing of data over time leads to the concept of Big Data which involves not only the structured but also unstructured data such as images, audio, video, and other data formats. Encrypting such varied and immense data is a challenge in itself. In this paper, we delve into some of the major algorithms and techniques for efficient encryption and decryption of the data. Moreover, we have also done a comparative analysis of the different encryption and decryption techniques to predict the use of these techniques based on application requirements. The main objective of this work is to convey a better focus on data encryption approaches and to bring out the major issues and application areas where these encryption algorithms best suit.

Since Rijndael algorithm was selected as the Advanced Encryption Standard (AES) by NIST, optimization research for the AES has been actively conducted on various IoT-based processors. In an 8-bit AVR environment, LIGHT version of Fast AES CTR-mode Encryption (FACE-LIGHT) was proposed at ICISC’2019 conference. However, in a Wireless Sensor Network environment, where sessions are frequently changed, FACE-LIGHT seems not efficient in terms of available memory and generating a pre-computation table. In this article, we present a new column-wise fashion implementation. Unlike previous best AES implementations, our proposed implementation in an 8-bit AVR microcontroller combines SubBytes, ShiftRows, and MixColums operations and optimizes the operation speed through efficient register scheduling. Our constant-time implementation uses a significantly less table than FACE-LIGHT in an 8-bit AVR microcontroller, achieving 2,251, 2,706, and 3,160 clock cycles when encrypting 128-bit data for each of three security levels. In particular, our 256-bit security level AES implementation is the fastest AES implementation as far as we know in 8-bit AVR microcontroller. Finally, we apply our implementation in CounTeR-mode_Deterministic Random Bit Generator (CTR_DRBG), one of the upper algorithms of a symmetric-key algorithm, to prove the generality of our optimization technology in various operating modes of AES.

Cloud storage with sharing services is increasingly popular among data owners. However, it is difficult for the users to know if the cloud server providers (CSPs) indeed protect their data. To verify data integrity and preserve data and key privacy in the group, this paper proposes a new threshold hybrid encryption for integrity auditing method without trusted center. The proposed method is developed based on the Advanced Encryption Standard (AES) and the Elliptic Curve Cryptography (ECC) with Shamir secret sharing. In this way, the key can be distributed and managed without trusted center, preserving the privacy of the key of the AES and users’ private key. Besides, we design and implement a novel integrity auditing and re-signature method which verifies the data integrity and solves the collusion question of the cloud and the revoked users. Security analysis and performance evaluation demonstrate that the proposed scheme realizes the correctness, security, and efficiency with a low communication and computation cost.

Along with features of the architecture of a textual DBMS with associative protection, problems of encoding text characters and generating a protected database using encoded text are considered in the context of an earlier infological database for the associative protection of text messages. The steganographic resistance of associative protection is assessed using the NIST (National Institute of Standards and Technology) set of statistical randomness tests. It is shown that the steganographic resistance of the approach is unconditional if certain conditions are met by lengthening the time for generating steganographic messages. The rates of concealing and decrypting associative steganographic text are compared to those of the modern Russian cryptosystem (the Kuznyechik cipher) and the AES (Advanced Encryption Standard) cryptosystem.

One way hash chain with a new key indicating the performance of the node as well to isolate malicious nodes from the network. Public key cryptography is derived using elliptical curve cryptography (ECC) have couple of key for decryption and encryption. Public key cryptography provides protection and verification using numerous algorithms. In addition secret session key is generated for secured data transmission and improve energy efficiency in WSN. Advanced encryption standard (AES) is applied for message cipher text once the key validation process gets finished. Energy proficient hybrid secure scheme (EPHSS) is proposed to provide secured and energy efficient data transmissions in WSN. To utilise the node energy in a proper way node clustering process is carried out. Clustering process efficiently reduces unnecessary energy wastage during node communication. Graded co-prime keys are generated for public and private keys, also encrypting functions are performed for providing security mechanisms. This mechanism improves security measures and simultaneously reduces energy consumption among nodes. The route should be undetectable by malicious nodes and the data should not be lacerate by the opponent node even it gets to know the public key. Identifying private key component [B, n] is difficult for malevolent; thus building it computationally infeasible for discovering decryption type at receiver side. Simulation presentations of the networks are analysed by network simulator tool. Efficiency of the proposed scheme is computed by taking delivery rates of packets which results in 18% better than the conventional ECCSAS scheme.

Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128 encryption iterative architecture is designed to achieve minimum area and less hardware utilization. Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. Furthermore, hardware utilization is minimized by incorporating the Vedic multiplier in the Mix column transformation of the AES Encryption process. The proposed encryption architecture is of 128-bit size and was executed on the Xilinx Spartan FPGA series, namely, Spartan 3, Virtex-4 and Virtex-5 devices. The optimization result exhibits that the proposed S-box technique has a smaller area than other existing conventional works.

Security-critical applications on integrated circuits (ICs) are threatened by probing attacks that extract sensitive information assisted with focused ion beam (FIB)-based circuit edit. Existing countermeasures, such as active shield, analog shield, and $t$ -private circuit, have proven to be inefficient and provide limited resistance against probing attacks without taking FIB capabilities into consideration. In this article, we propose an FIB-aware anti-probing physical design flow, which considers FIB capabilities and utilizes computer-aided design (CAD) tools, to automatically reduce the probing attack vulnerability of an IC’s security-critical nets with minimal extra design effort. The floor-planning and routing of the design are constrained by incorporating three new steps in the conventional physical design flow, so that security-critical nets are protected by internal shield nets with low overhead. Results show that the proposed technique can reduce the vulnerable area exposed to probing on security-critical nets by 100% with all critical nets fully protected for both advanced encryption standard (AES) and data encryption standard (DES) modules. The timing, area, and power overheads are less than 3% per module, which would be negligible in a system-on-chip (SoC) design.

This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal of this study is to design a high throughput and FPGA efficiency (FPGA-Eff) cryptosystem for high-traffic applications. To achieve high throughput, loop-unrolling, inner and outer pipelining techniques are employed. In AES, substitution bytes (Sub-Bytes) is one of the costly functions that occupy a large number of resources and has a large delay. To reduce the area of Sub-Bytes, new-affine-transformation, which is the combination of inverse isomorphic and affine transformation, is proposed and employed. Besides that, AES has been modified according to the proposed architecture. For the first nine rounds, Shift-Rows and Sub-Bytes have been exchanged, and Shift-Rows is merged with Add-Round-Key. To make an equal latency between stages, Mix-Columns is divided into two different stages. AES is implemented in counter mode on Xilinx Virtex-5 using VHDL. The proposed implementation achieves a throughput of 79.7 Gbps, FPGA-Eff of 13.3 Mbps/slice, and frequency of 622.4 MHz. Compared to the state-of-the-art work, the proposed design has improved data throughput by 8.02% and FPGA-Eff by 22.63%.

The tremendous growth of computational clouds has attracted and enabled intensive computation on resource-constrained client devices. Predominantly, smart mobiles are enabled to deploy data and computational intensive applications by leveraging on the demand service model of remote data centres. However, outsourcing personal and confidential data to the remote data servers is challenging for the reason of new issues involved in data privacy and security. Therefore, the traditional advanced encryption standard (AES) algorithm needs to be enhanced in order to cope with the emerging security threats in the cloud environment. This research presents a framework with key features including enhanced security and owner’s data privacy. It modifies the 128 AES algorithm to increase the speed of the encryption process, 1000 blocks per second, by the double round key feature. However, traditionally, there is a single round key with 800 blocks per second. The proposed algorithm involves less power consumption, better load balancing, and enhanced trust and resource management on the network. The proposed framework includes deployment of AES with 16, 32, 64, and 128 plain text bytes. Simulation results are visualized in a way that depicts suitability of the algorithm while achieving particular quality attributes. Results show that the proposed framework minimizes energy consumption by 14.43%, network usage by 11.53%, and delay by 15.67%. Hence, the proposed framework enhances security, minimizes resource utilization, and reduces delay while deploying services of computational clouds.

Satellite images have key features such as; large data size, strong correlation between adjacent pixels and high redundancy. Unfortunately, traditional operation modes used to implement the Advanced Encryption Standard (AES) encrypt data without taking into account these specific image features. As a result, the traditional modes are not suitable for image encryption. In this paper, we present a robust satellite image encryption scheme based on discretized chaotic maps and AES. The discretized chaotic maps are used to achieve a confusion and key generation in order to improve the performance of security, especially the sensitivity to plain image. The simulation results show that the proposed technique presents attractive features, including a high level of security, large key space with improved sensitivities to key and plain image.

Ensuring protection against side channel attacks (SCAs) is a crucial requirement in the design of modern secure embedded systems. Profiled SCAs, the class to which template attacks and machine learning attacks belong, derive a model of the side channel behavior of a device identical to the target one, and exploit the said model to extract the key from the target, under the hypothesis that the side channel behaviors of the two devices match. We propose an architectural countermeasure against cross-device profiled attacks which differentiates the side channel behavior of different instances of the same hardware design, preventing the reuse of a model derived on a device other than the target one. In particular, we describe an instance of our solution providing a protected hardware implementation of the advanced encryption standard (AES) block cipher and experimentally validate its resistance against both Bayesian templates and machine learning approaches based on support vector machines also considering different state-of-the-art feature reduction techniques to increase the effectiveness of the profiled attacks. Results show that our countermeasure foils the key retrieval attempts via profiled attacks ensuring a key derivation accuracy equivalent to a random guess.

Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power by moving data through a sequence of pipelined registers. We present in this article a novel 8-bit AES architecture that solves data movement inefficiencies by renaming registers and saves clock power with a single state update per AES round. We then extend register renaming to include microarchitectural randomization to mitigate susceptibility to side-channel attacks, which are a concern especially for low power implementations of AES. We fabricate and evaluate our designs in a commercial 16-nm FinFET technology. Testchip measurements show that the register renaming architecture encrypts data at 0.55 pJ/bit at nominal voltage, a $2.2\times $ improvement over a state-of-the-art reference 8-bit design implemented in the same technology. Side-channel evaluation indicates that the randomized variant of register renaming significantly reduces vulnerability to differential power analysis (DPA).

A new symmetric cryptosystem is proposed in this paper which will be used to carry out image encryption without compression. The proposed system has been developed to encrypt images in BMP format. A significant contribution of this investigation is the use of one solution point of a zero valued constant elliptic curve in order to generate a set of 15 encryption keys. On the other hand, using a differential equation that produce chaotic numbers a permutation and its inverse permutation are generated. Every encryption key and both permutations are the same size as the image. The proposed cryptosystem is tested for the purpose of verifying its resistance against several cryptographic attacks as well as the randomness and quality of its ciphering. Results are showed and compared with some recent scientific articles published between 2017 and 2019.

Connected smart vehicles in automotive industries have increased, resulting in high vehicle-to-vehicle, vehicle-to-infrastructure, and vehicle-to-cloud connectivity. Increased data rates are required to achieve high bandwidth requirements to support such communication networks. Despite having numerous advantages, high connectivity between devices poses threats to vehicle and human security, rendering encryption critical before transmitting data across vehicular networks. Advanced encryption standard (AES) is commonly used for data encryption in automotive microcontrollers. Owing to modern digital design complexities, field-programmable gate arrays (FPGAs) are attracting attention for pre-silicon verification and software development. Owing to their parallel architectures, FPGAs are ideal for prototyping automotive designs running encryption algorithms, like AES at real-time data rates. Moreover, because they are reconfigurable, prototyping results of different implementation choices can be verified at an early stage, thereby helping architects and designers with forthcoming optimal designs. FPGAs also serve as platforms to develop software considerably before silicon arrives, thereby decreasing the time to market. Herein, we propose a high-throughput FPGA implementation of the AES algorithm for automotive microcontrollers using a 128-bit key created via Vivado high-level synthesis (HLS) tool. We use HLS design method based on application-specific bit widths to implement the design on FPGA. The generated design is implemented and verified using Xilinx Kintex 7 and Virtex 6 FPGA; despite identical resource utilization (Look up tables and Flip-Flops), the throughput results are superior to those obtained previously.

Due to the large-scale development in satellite and network communication technologies, there is a significant demand for preserving the secure storage and transmission of the data over the internet and shared network environments. New challenges appeared that are related to the protection of critical and sensitive datafrom illegal usage and unauthorized access. In this paper, we address the issues described above and develop new techniques to eliminate the associated problems. To achieve this, we propose a design of a new sensor node for tracking the location of cars and collecting all information and all visited locations by cars, followed byencryption in a sensor node and saving in the database. A microcontroller of Arduino esp8266 Node MCU board and a GPS module are used. The cryptography uses the chaos-based symmetric-key encryption technique for data. This scheme utilizes a chaotic map (Hénon map) for robustness and security of data. The key sensitivity can be performed by statistical experiments to determine the safety, reliability, and speed of the algorithm. The proposed algorithm presents several exciting features, such as a high level of security, sufficient saving of the energy of the sensor network, and an acceptable encryption speed compared to Advanced Encryption Standard (AES) and Data Encryption Standard (DES).

The proliferation of mobile phones with integrated sensors makes large scale sensing possible at low cost. During mobile sensing, data mostly contain sensitive information of users such as their real-time location. When such information are not effectively secured, users’ privacy can be violated due to eavesdropping and information disclosure. In this paper, we demonstrated the possibility of unauthorized access to location information of a user during sensing due to the ineffective security mechanisms in most sensing applications. We analyzed 40 apps downloaded from Google Play Store and results showed a 100% success rate in traffic interception and disclosure of sensitive information of users. As a countermeasure, a security scheme which ensures encryption and authentication of sensed data using Advanced Encryption Standard 256-Galois Counter Mode was proposed. End-to-end security of location and motion data from smartphone sensors are ensured using the proposed security scheme. Security analysis of the proposed scheme showed it to be effective in protecting Android based sensor data against eavesdropping, information disclosure and data modification.

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p–i–n forward current with an increase in negative drain-to-source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p–i–n forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S-box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S-box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET-based circuits and systems.

Memory resistor or memristor is the fourth fundamental circuit element that has attained considerable attention due to its unique characteristics and possible extensive applications in future generation nanoscale circuits and systems. In this brief, the contribution that memristor-based circuits may offer to the evolution of cryptographic hardware and embedded systems is discussed. Specifically, it will be shown how memristor-based implementation of security algorithms can mitigate the danger of differential power analysis attacks (DPAs) at the technology level with lower cost and energy compared to conventional existing algorithmic countermeasure techniques. A 128-bit Advanced Encryption Standard (AES) cryptoprocessor was designed and implemented in both CMOS and hybrid CMOS/memristor technology. The robustness of the CMOS-based implementation against power analysis attacks was evaluated on Side-Channel Attack User Reference Architecture (SAKURA-GII) while the nanoscale counterpart system was evaluated by using a customized simulation and attack environment which was developed for extracting power traces using Synopsys and Cadence tools along with a DPA attack software implemented in MATLAB. It was observed that hybrid CMOS/memristor-based implementation provides considerable improvement over implementation with regular CMOS architectures in terms of energy consumption and attack tolerance and demonstrates good potential in mitigating DPA attacks without having to apply costly countermeasures such as masking or hiding.

Scan chain is an architectural solution to facilitate in-field tests and debugging of digital chips, however, it is also known as a source of security problems, e.g. scan-based attacks in the chips. The authors conduct a comprehensive gate-level security analysis on crypto-chips, which are equipped with a scan chain, and then propose a set of protection mechanisms to immune vulnerable nets of the chips against scan-based attacks. After extracting the set of most vulnerable nets, they perform net pruning algorithms on them, and gate-level protection mechanisms to block the information leaking from the nets during test mode. The protection mechanisms employ net masking, net flipping, and net shuffling based on the specifications of every net, i.e. gate-type driving the net, fan-out of the net, and net's logical depth. Their evaluations on the hardware-implemented advanced encryption standard (AES) and data encryption standard (DES) encryption algorithms show 100% for all types of scan-based attack tolerance, while the area overhead is at most 1.5%, 6.1% for AES and DES crypto-chip, respectively. As they find the smallest set of nets that have a high contribution to the scan attack, the test coverage loss of their protection mechanism is evaluated to be

Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

Cloud data storage is a service offered by cloud computing for storing the data. Though it has a lot of benefits, the security of the stored data is one of its major concerns. Many models have been developed to address this issue. These models encrypt the data and store them. Advanced encryption standard (AES) is one of the encryption methods that has been used prevalently. This paper presents a model that tries to further strengthen the AES algorithm. It alters the shift row of the AES by making it key dependent. The key dependency enhances the security of the algorithm and the results show that the statistical pattern of the plaintext is dispersed over the cipher text, thereby, defending the plaintext from the cryptanalysis. Experimental results indicate that the dispersion ratio of the plaintext over the cipher text increases from 0.75 for AES to approximately 1 for the proposed model. The model is also analyzed using the coefficient of variation metric. The proposed model also exhibits a significant level of avalanche effect.

The last few years have witnessed a vast evolution in the communication and computational fields. The presence of social media makes data transferring more easier, which raises a flag of unauthorized usage and redistribution of digital contents. This copyright scenario is hardly affecting the publishing rights of authors and publishers. This paper presents a robust framework that protects the copyright property where only the authorized users legally use the data and prevents the illegal using or copying of data. The proposed framework is based on Digital Right Management (DRM) and includes two robust cryptosystems; Advanced Encryption Standard (AES) and Elliptic Curve Cryptography (ECC) algorithms. The multimedia contents are encrypted using the AES-256 algorithm, while the shared key is encrypted using the ECC algorithm. The authorized user can utilize the copyrighted contents if the authorization is not expired. The license generation is done by a lightweight data-interchange format JavaScript Object Notation (JSON), and the license is validated using the Elliptic Curve Digital Signature Algorithm. The evaluation of the system has shown that it is fulfilling all the requirements of DRM technology with low cost, availability, platform independently, reliability and scalability since it is implemented on a cloud platform.

Sensitive data need to be protected from being stolen and read by unauthorized persons regardless of whether the data are stored in hard drives, flash memory, laptops, desktops, and other storage devices. In an enterprise environment where sensitive data is stored on storage devices, such as financial or military data, encryption is used in the storage device to ensure data confidentiality. Nowadays, the SSD-based NAND storage devices are favored over HDD and SSHD to store data because they offer increased performance and reduced access latency to the client. In this paper, the performance of different symmetric encryption algorithms is evaluated on HDD, SSHD, and SSD-based NAND MLC flash memory using two different storage encryption software. Based on the experiments we carried out, Advanced Encryption Standard (AES) algorithm on HDD outperforms Serpent and Twofish algorithms in terms of random read speed and write speed (both sequentially and randomly), whereas Twofish algorithm is slightly faster than AES in sequential reading on SSHD and SSD-based NAND MLC flash memory. By conducting full range of evaluative tests across HDD, SSHD, and SSD, our experimental results can give better idea for the storage consumers to determine which kind of storage device and encryption algorithm is suitable for their purposes. This will give them an opportunity to continuously achieve the best performance of the storage device and secure their sensitive data.

This paper proposes an ultra-low-power multi-mode baseband transceiver for capsule endoscopy. We set a new specification for capsule endoscopy to achieve ultra-low power and short-latency transceiver. The proposed baseband transceiver can operate multi-mode to transmit ten images per seconds depending on the presence of the lesion and the position of the capsule endoscope. The proposed one does not require memory and optimized all the logic and architecture levels. The proposed BCH decoder uses the early termination scheme to reduce the 51.16% of latency and 45.78% of power consumption, respectively. In addition, the advanced encryption standard (AES) processor protects the biomedical information. As a result, we implemented the proposed multi-mode baseband in Verilog-HDL and synthesized by using the Samsung 65 nm CMOS standard cell library. The proposed baseband shows 10.07 μW (0.9 V, @10 MHz) of total power consumption.

In this digital information era, data transmitted over internet is vulnerable to several types of attacks. To preserve our information over internet, it is necessary to use some cryptographic methods. advanced encryption standard is a strong symmetric, non-fiestel cryptographic algorithm which preserves the information transmitted in internet from piracy or attacks. In this research article, a new and an efficient key dependent AES algorithm is presented for securing the data over internet or digitally stored in any remote location. This proposed work gives better avalanche effect and strict avalanche effect on comparing with the original existing AES algorithm. Results of the proposed algorithm are obtained after testing 1000 pairs of samples of different secret key. And it shows that 58% of the times, new proposed algorithm have better avalanche effect than the existing algorithm.