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We present a compact, all-solid-state, low-cost quantum random number generator (QRNG) based on a single-photon avalanche diode (SPAD) and a field programmable gate array (FPGA). A new algorithm for random bit generation is described, ranking the inter-arrival times of a group of $M$ photons detected by the SPAD device, and processed directly on the FPGA. The proposed approach improves the efficiency of generated random bits per detected photon, spanning from 0.5 bits/photon in case of 0 order rank, up to 0.875 bits/photon for second order rank. By extending the algorithm to higher orders, the proposed system approaches the maximum theoretical value of 1.0 bit/photon. The rate of generation of random numbers is limited by the SPAD minimum deadtime, achieving an experimentally proven bit rate of 7.3 Mbps. The standard randomness statistical tests are passed for a wide range of photon fluxes and for all the implemented rank orders with no additional post-processing on the generated sequence.

We present a Montecarlo simulator developed in Matlab&reg, for the analysis of a Single Photon Avalanche Diode (SPAD)-based Complementary Metal-Oxide Semiconductor (CMOS) flash Light Detection and Ranging (LIDAR) system. The simulation environment has been developed to accurately model the components of a flash LIDAR system, such as illumination source, optics, and the architecture of the designated SPAD-based CMOS image sensor. Together with the modeling of the background noise and target topology, all of the fundamental factors that are involved in a typical LIDAR acquisition system have been included in order to predict the achievable system performance and verified with an existing sensor.

We present a field-programmable gate array (FPGA) implementation of a time-to-digital converter (TDC) based on a low-cost, low-area Spartan 6 device. The converter is based on a tapped delay line model. Several implementation details are discussed with a particular focus on critical blocks such as the input stage and thermometer-to-binary decoding techniques. We implemented a tap filtering technique to improve the differential nonlinearity (DNL) of the single delay line while keeping a good LSB value of 25.57 ps with a single-shot precision (SSP) between $0.69\div 1.46$ LSB. Measured DNL and integral nonlinearity (INL) lie in the range between $-0.90\div 1.23$ and $-0.43\div 2.96$ LSB, respectively. Measured DNL and INL lie in the range between $-0.90\div 1.23$ and $-0.43\div 2.96$ LSB, respectively. We then implemented an interpolating TDC to overcome the limitations of a single delay line in terms of linearity and measurement range. The interpolating TDC uses the sliding scale technique, where the time interval to be measured is asynchronous with respect to the FPGA clock, achieving DNL and INL in the range $-0.072\div 0.070$ and $-0.755\div 0.872$ LSB. SSP is in the $1.096\div 2.815$ range. Moreover, we present a novel comparison between the DNLs obtained with two different methods: statistical code density test and using a finely controlled delay source. Finally, we present the results of a Monte Carlo simulation used to investigate the effects of nonlinear propagation of the signal through the delay line.