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In this paper, we have analyzed the effect of high-k dielectrics in the tunneling barrier of bandgap engineered Silicon Oxide Nitride Oxide Silicon (BE-SONOS). The high-k materials used, hereby, are scandates and aluminates of the rare earth materials such as GdScO, LuAlO, and LaAlO. These materials have high permittivity and low valence band offset that helps in improving the erase speed and retention trade-off. Also, lower conduction band offset of these high-k dielectrics leads to the improvement of program speed. Here, scandate of the rare earth material, GdScO, substitutes the nitride (SiN) layer and the aluminates of the rare earth material, LuAlO and LaAlO, are used in place of top oxide (SiO2) layer in tunneling barrier (SiO2/SiN/SiO2) of BE-SONOS. Further, with the scaling of the gate length; for the same effective oxide thickness, it has been observed that the investigated stacks encompass the same memory dynamics as before the gate length scaling. Consequently, the investigated tunneling barrier stacks represent robustness in terms of retention (at room temperature and 150 oC) and enhanced program speed as well as erase speed and retention trade-off.

High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

the reliability and toughness of any SRAM cell is tarnished by miniaturization of device technology because of exponential increase in leakage current components in semiconductor devices. This article presents a novel SRAM cell topology to improve the standby leakage power dissipation, by dynamically varying the Cell Ratio and Pull-up ratio using wordline. The entire SRAM cell evaluation is performed at 45nm CMOS Technology. The standby leakage power dissipation of novel design is reduced to 63% as compared to standard six transistor based SRAM cell (6T). The read mode noise margin of novel design becomes 1.056× times than 6T SRAM cell. Further, the effect of process variation also considered for simulation. It also verifies that the novel design offers 8.30nW average (or mean) standby leakage power dissipation as compared to 13.60nW in 6T.

Aggressive technology scaling has inevitably led to reliability becomes a major concern for modern high-speed and high-performance integrated circuits. The major reliability concerns in nanoscale very-large-scale integration design are the time-dependent negative bias temperature instability (NBTI) degradation. Owing to increasing vertical oxide field and higher operating temperature, the threshold voltage of P-channel MOS transistors increases with time under NBTI. This study presents a novel subthreshold Darlington pair-based NBTI degradation sensor under the stress conditions. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The Darlington pair used in the circuit provides the stability and the high-input impedance of the circuit makes it less affected by the process variations. Owing to high sensitivity, the proposed sensor is best suited for sensing of temperature variation, process variation, and temporal degradation during measurement. The sensitivity of the proposed sensor at room temperature is 0.239 mV/nA under subthreshold conditions. The proposed sensor is less affected by the process variation and has the maximum deviation of 0.0011 mV at standby leakage current of 30 nA.

Negative bias temperature instability (NBTI) is a major time-dependent reliability concern with the pMOS transistor at elevated temperature. NBTI in pMOS is the severe dominating factor of circuit reliability as it increases the threshold voltage with time. In this paper, an nMOS-only Schmitt trigger with a voltage booster (NST-VB) circuit is proposed. The use of only an nMOS transistor in the critical path of the Schmitt trigger circuit drastically reduces the effect of NBTI on the circuit and, hence, improves performance. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of an nMOS-only structure. Because of NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% compared to 7.2% and 1.47% for the conventional Schmitt trigger and nMOS inverter, respectively, after the stress time of three years. The proposed NST-VB circuit is also validated with an s27 benchmark circuit from the ISCAS’89 benchmark set and found that it has a lower effect of NBTI compared to CMOS and Schmitt trigger inverter circuits. For the viability of the proposed circuit, figure-of-merit (FOM) is used as a performance metric and it is found that the proposed circuit has ${15.11\times }$ improved FOM compared to the conventional Schmitt trigger circuit.

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.

As an alternative to conventional tunnel field-effect transistor (TFET) devices for low-power applications, drain-underlap (DU) cylindrical (Cyl) gate-all-around (GAA) TFETs based on a Ge source using fringing-field effects can show suppressed subthreshold leakage current. In this work, such a fringing field is implemented using a hetero-spacer dielectric placed over the Ge source, resulting in enhanced direct-current (DC) and analog/radiofrequency (RF) characteristics such as $$I_{\mathrm{ON}}$$ , $$I_{\mathrm{OFF}}$$ , subthreshold swing (SS), $$C_{\mathrm{gs}}$$ , $$C_{\mathrm{gd}}$$ , and $$f_\mathrm{t}$$ . It is found that the ambipolar behavior and Miller capacitance $$C_{\mathrm{gd}}$$ are minimized in combination with a high band-to-band tunneling (BTBT) rate compared with devices based on a homo-spacer dielectric placed over a Si source. At the same time, the drain-underlap design increases the series resistance across the drain–channel junction overlapped by the fringing field, reducing $$I_{\mathrm{OFF}}$$ . Furthermore, the performance of the proposed device matches well with experimental data when including the effects of trap-assisted tunneling (TAT) for improved device reliability. Thus, the behavior of the RF figure of merit of the proposed device is different compared with conventional TFET designs.

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of pMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin, and word line write margin (WLWM). The O-ABB consists of standby leakage current ( ${I}_{{ddq}}$ ) sensor circuit, decision circuit, and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of ten years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM, and WLWM decreases by 10.55%, 8.55%, and 3.25%, respectively, in the absence of O-ABB, whereas hold SNM, read SNM, and WLWM decreases by only 0.47%, 1.15%, and 0.62%, respectively, if O-ABB is used to compensate the degradation.

A unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on hetero-spacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as I ON, I OFF, SS, I ON /I OFF, C gs, and C gd have been investigated, while included TAT model and compared the examined device with AU GAA-TFET based on homo-spacer (HS) dielectric. On the basis of observation, the proposed device increases ON current as high as 2.1 × 10−6 A/µm, which corresponds to 1024 times improvement in I ON /I OFF when compared with device based on HS. It also suppresses ambipolar behaviour with fast switching ON–OFF transition due to low leakage current (I OFF). These performances are mainly produced due to AU and low-k spacer dielectric which is replaced by high-k dielectric over source side spacer of the device, whereas drain side spacer is placed with high-k material along with increase in series resistance across drain–channel junction caused by drain underlap. Low-k spacer reduces the fringing field, and the depletion does not form at the source–gate edge, hence high source–channel tunnelling junction.

A novel N-type MOS (NMOS) only Schmitt trigger with voltage booster (NST-VB) circuit is presented. The proposed NST-VB circuit uses NMOS transistors in both pull-up and pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35 × and 3.53 × improved FOM as compared with the conventional Schmitt trigger and NMOS inverter, respectively.

In this paper, the spiking neural network has been implemented by using 3D tunneling device based on SiGe as a source for circuit applications. Here, Device circuit co-design investigations have been made in terms of device characteristics and circuit parameters using Synopsys 3D TCAD software and HSPICE simulation. The implemented circuit minimizes the spiking time with the help of tunneling transistors. The proposed tunneling device use the merits of low band gap material such as SiGe, used as a material in the source region with low spacer width, reduces the depletion of the fringing field over source gate edge, leads to high (\(I_{ON}\)). Whereas, drain underlap increases the drain channel resistance, and significantly reduces leakage current (\(I_{OFF}\)). The spiking neural network circuit has been simulated by applying the test signal at the excitatory input to the benchmark circuit and observe the output response at the inhibitory node, it has a quick response and efficient spiking pulse train with negligible leakage current.

An efficient FPGA or ASIC based hardware implementation of deep neural networks face the challenge of limited chip area, and therefore an area efficient architecture is required to fully harness the capacity of parallel processing of FPGA and ASIC in contrast to general purpose processors. In literature, the challenges are to investigate a generalized mathematical model and architecture for neuron block in an ANN implementation. We have proposed a generalized architecture for neuron implementation based on the shift-and-add algorithm, collectively known as Coordinate Rotation Digital Computer (CORDIC) algorithm, having a wide range of application. The look-up-table (LUT) based approach with a shift-and-add algorithm is an alternative technique for polynomial approximation and implementation. Paper explains how the CORDIC algorithm works and investigates the power and area efficient versatile computational unit for ANN application. The derived model proves that for the hyperbolic tangent function required a double pseudo-rotation and additional subtraction compares to the sigmoid function. In this reference versatile approach based optimized sigmoid activation function is implemented. The function is synthesized and validate on Xilinx zynq XC7Z010clg400 SoC and result reveals the minimum resources utilization.

A comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high I ON (6.9 × 10−4 A/µm), low I OFF (2.5 × 10−17 A/µm), and an enhanced I ON/I OFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET.

This paper presents a Cylindrical GAA TFET based on germanium source for low power applications. The proposed device used the merits of low band gap material such as germanium, which is used as a material in the source region. Device investigations have been made in terms of DC characteristics like I ON , I OFF , SS, I ON /I OFF . The proposed device increases ON-current as high as 1.9 × 10−5 A/μm, which corresponds to 7 × improvement in I ON /I OFF ratio when compared with the Si-GAA-TFET. Whereas, drain underlap causes increase in series resistance across drain-channel junction, which reduces the electric field by increasing the tunneling barrier width at the drain side, significantly reduced off-state leakage current. This shows the better device performance to address the requirement of ultra-low power applications.

This paper presents a novel subthreshold Darlington pair based negative bias temperature instability (NBTI) monitoring sensor under the stress conditions. The Darlington pair used in the circuit provides the stability of the circuit and the high input impedance of the circuit makes it less affected by the PVT variations. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The sensitivity of the proposed sensor is 8.15 μV/nA and also the sensor is less affected by the process variation and has the deviation of 0.0011 mV at standby leakage current of 30 nA.

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device.