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Fan-Out enables new heterogeneous packaging concepts where chips are embedded in an electronic mold compound (EMC) package with ultra-small footprint. These multi-chip systems demand a high routing density in the redistribution layer (RDL) which is realized by fine copper features with line and space structures in the dimension down to 2 μm, establishing electrical interconnects between the chips across different substrate materials (e.g. silicon chips and mold-filled gaps). The copper lines undergo high mechanical stress due different thermal expansion coefficients of the used materials. Numerous papers investigated reliability topics only focusing on properties of the polymer in the redistribution layer and the solder ball material, but the influence of the mechanical properties of electroplated copper has been a minor topic so far [1] [2] [3].With feature sizes and thicknesses of about 2 μm, these structures are in the range of copper grain size with the result that different grain structures become more important. Also, the material suppliers start to tune galvanic copper baths to generate e.g. twinned copper structures with mechanically superior behavior. Characterizing these fine structures at that scale is challenging because the properties could be different compared to macro samples. This work presents an on-wafer characterization method of copper features down to 2 μm with a newly designed wafer scale micro tensile test. This concept allows a test integration in the fab process flow. The elongation at break and the tensile strength of ultra fine line copper lines are measured by the tensile loading. The results are compared with macro scale tensile tests.

A novel capacitive sensor for measuring the water-level and monitoring the water quality has been developed in this work by using an enhanced screen printing technology. A commonly used environment-friendly conductive polymer poly(3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) for conductive sensors has a limited conductivity due to its high sheet resistance. A physical treatment performed during the printing process has reduced the sheet resistance of printed PEDOT:PSS on polyethylenterephthalat (PET) substrate from 264.39 Ω/sq to 23.44 Ω/sq. The adhesion bonding force between printed PEDOT:PSS and the substrate PET is increased by using chemical treatment and tested using a newly designed adhesive peeling force test. Using the economical conductive ink PEDOT:PSS with this new physical treatment, our capacitive sensors are cost-efficient and have a sensitivity of up to 1.25 pF/mm.

The Fan-Out Wafer Level Packaging (FOWLP) is one of the biggest impacts for the microelectronics packaging today. Main benefit is the high potential in significant package miniaturization by the substrate-less short interconnects, which are realized by thin film metallization directly on the embedded dies instead of wire bonding or flip chip - bumps. This allows a cost effective and robust generation of multi-chip packages for System in Package (SiP) solutions. The thickness of the FOWLP's which are in volume production is in the range of 300 to 400 um [1]. The stacking of FOWLP packages for higher integrations set demands for thinner packages. Main limitation for high volume production of packages below 300 um is the handling of the thin substrates during the processing and the assembly of thin and also warped packages. This paper presents an innovative concept (Hybrid Fan-Out - hFO) for generation and handling of thin FOWLP substrates. A fundamental process change is realized in the so called chip-first approach which enables packages with thickness down to 30 um and below. The mold-first approach based on the assembly of dies on a thermal release tape, which is followed by the embedding process. The epoxy mold compound (EMC) substrate with the embedded dies is released from the carrier by peeling of the TRT and the redistribution layer (RDL) is generated. For the new approach the dies are directly assembled on a glass carrier with a die adhesive. The temperature stable bond of the dies to the glass carrier enables a thinning and backside processing of the EMC / glass carrier stack. The embedded dies are coincidently thinned together the mold material with the benefit, that no thinned dies are demanded for generation of thin packages and simplifies the assembly process. A RDL process is applied on the backside, which stabilize the ultra-thin package. A ultra-fine routing layer could realized because the stiff glass carrier inhibits any EMC substrate deformation or length changes, like it is happen by cure shrinkage or humidity uptake. The RDL on the front side is generated after the release from the carrier. The symmetric build-up structure with an EMC core and a double sided RDL allows to increase the number of routing layers, which are demanded for shielding and supply layers for RF applications. FOWLP packages with a thickness down to 50 um are demonstrated in this paper.

The demands of higher routing density on wafer level are driven by multi-chip integrated fan-out packages and high I/O CSPs. New technologies and materials are necessary to generate lines and spaces down to 2 µm. Multi-metal layers are necessary for the higher wiring effort on panel level packaging (PLP) for example to contact dies which are embedded together. This places higher demands on the mechanical properties of the materials that are used for the redistribution layer. This paper presents a new excimer laser-enabled dual damascene process for ultra-fine routing for BEOL which was developed in a joint project with SUSS MicroTec. In the project, various materials e.g. low temperature cure polyimide, BCB and dry-film ABF materials were structured by using an excimer laser stepper with a reticle mask to pattern feature sizes below 4 µm with a high throughput. Micro-vias with a diameter below 5 µm were ablated with an aspect ratios up to 4 which is exceeding the photolithographic resolution limits of the established photosensitive thin-film polymers. The laser structuring allows the usage of innovative dielectric materials for WLPs/PLPs with optimized mechanical and electrical parameters, for example polymers with inorganic fillers like dry-film ABF material. Also, the ablations depth per laser pulse was investigated. The ablated lines and micro-vias were metallized by applying a galvanic process and CMP. The stepper-like system allows a sub-micron alignment accuracy with no need of a capture pad in the redistribution layers. Test multi-layer structures have been designed and fabricated with lines and spaces below 10 µm to demonstrate the dense routing capability with an excellent reliability which was verified by air-to-air thermal cycling (from -55 °C up to 125 °C).