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With the rapid development of general hardware technology, microcomputers with multi-core CPUs have been widely applied in commercial services and household usage in the last ten years. Multi-core chips could, theoretically, lead to much better performance and computational efficiency than single-core chips. But so far, they have not shown general advantages for users, other than for operating systems and some specialized software. It is not easy to transform traditional single-core-based algorithms into multi-core-, multi-thread-based algorithms that can greatly improve efficiency, because of difficulties in computation and scheduling of hardware kernels, and because some programming languages cannot support multi-core, multi-thread programming. Therefore, a kind of multi-core-, multi-thread-based fast algorithm was designed and coded with Delphi language for the medium- and large-scale traveling salesman problem instances from TSPLIB, which can fully speed up the searching process without loss of quality. Experimental results show that the algorithm proposed can, under the given hardware limitations, take full advantage of multi-core chips and effectively balance the conflict between increasing problem size and computational efficiency and thus acquire satisfactory solutions.

With the smooth upgrade of the access network, multiple tuning-time devices will coexist in the long-reach access network, and the subsequent problems of high round-trip time (RTT) and optical network unit (ONU) tuning delay need to be solved urgently. In this paper, a multi-thread multiple tuning-time devices coexistence (MT-MTDC) bandwidth allocation algorithm is proposed. This algorithm can solve the problems of high RTT and ONU tuning delay in virtual passive optical network (VPON) based on long-reach wavelength division multiplexing/time division multiplexing passive optical network (LR WDM/TDM PON). Firstly, Multi-threaded polling mechanism is introduced into multi-mode coexistence VPON. Next, the number of wavelengths and threads is selected adaptively to ensure high bandwidth utilization. Then, the mechanism of dynamically adjusting the thread window is proposed. The mechanism strengthens the collaboration ability between threads and solves the degradation problem of the multi-thread algorithm. Furthermore, the construction of tuning buffer and the setting of time flag effectively solve the problem of more frequent ONU tuning pressure and ONU transmission conflict caused by multi-threaded polling algorithm. Finally, by comparing with the multi-thread longest-first first-available (MT-LFFA) algorithm and the multi-tuning-time ONU scheduling (MOS) algorithm, the proposed algorithm demonstrates its effectiveness in terms of polling cycle time, average tuning delay, bandwidth utilization and average packet delay.

Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA), (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

Finite-element method (FEM) has been widely used in industrial applications for many years. With the increase of finite-element model complexity and the number of elements, computation burden has become a serious issue and requires more attention. In this paper, the transmission line method (TLM) is adopted to the solution of FEM-based nonlinear axisymmetric magnetostatic problem and an equivalent finite-element network’s circuit model is given. Several methods were investigated to speed up the computation, such as Newton preconditioners, simplification of nonlinear equation solution and parallel computation. Compared with traditional Newton FEM iteration, our results show that the proposed method has more obvious advantages on computational efficiency at the same calculation accuracy. The method is applicable and valuable in the characteristic analysis and design of the magnetic device with a cylindrical structure.

International audience; The use of multi-core processors will become a trend in safety critical systems. For safe execution of multithreaded code, automatic code generation from formal specification is a desirable method. Signal, a synchronous language dedicated for the functional description of safety critical systems, provides soundness semantics for deterministic concurrency. Although sequential code generation of Signal has been implemented in Polychrony compiler, deterministic multi-threaded code generation strategy is still far from mature. Moreover, existing code generation methods use certain multi-thread library, which limits the cross platform executions. OpenMP is an application program interface (API) standard for parallel programming, supported by several mainstream compilers from different platforms. This paper presents a methodology translating Signal program to OpenMP-based multi-threaded C code. First, the intermediate representation of the core syntax of Signal using synchronous guarded actions is defined. Then, according to the compositional semantics of Signal equations, the Signal program is synthesized to dependency graph (DG). After parallel tasks are extracted from dependency graph, the Signal program can be finally translated into OpenMP-based C code which can be executed on multiple platforms.

International audience; Many linear algebra libraries, such as the Intel MKL, Magma or Eigen, provide fast Cholesky factorization. These libraries are suited for big matrices but perform slowly on small ones. Even though State-of-the-Art studies begin to take an interest in small matrices, they usually feature a few hundreds rows. Fields like Computer Vision or High Energy Physics use tiny matrices. In this paper we show that it is possible to speedup the Cholesky factorization for tiny matrices by grouping them in batches and using highly specialized code. We provide High Level Transformations that accelerate the factorization for current Intel SIMD architectures (SSE, AVX2, KNC, AVX512). We achieve with these transformations combined with SIMD a speedup from 13 to 31 for the whole resolution compared to the naive code on a single core AVX2 machine and a speedup from 15 to 33 with multithreading compared to the multithreaded naive code.

Chenille yarns are vulnerable to abrasion because of easy pile loss. In this study different chenille yarns were produced from sirospun and two-folded ring, 100% wool and 50% wool-50% polyester blend yarns of different fiber fineness. A yarn abrasion device was designed in order to measure the abrasion resistance of chenille yarns and the abrasion resistance of knitted fabrics made from these yarns was measured with a Martindale Abrasion tester. In addition, chenille yarns abraded for different numbers of abrasion cycles were analyzed using a computerized image analysis method to evaluate the abrasion behavior. The results were analyzed statistically. According to the results, the use of wool blends and sirospun yarns as pile materials led to an improvement in abrasion resistance. Correlation analyses confirmed strong linear relationships with high values of correlation coefficients (above 0.9) between the mass loss values obtained from abrasion tests and the abrasion coefficients of the chenille yarns obtained from image analysis.

The effects of chenille yarn properties—pile material type, pile length, and twist level—on the boiling shrinkage behavior of chenille yarns are examined in this study. Different chenille yarns are produced on a chenille machine using a range of pile material types, twist levels, and pile lengths. Nm 4 and Nm 6 count chenille yarns are produced from different pile materials of viscose, acrylic (0.9 dtex), acrylic (1.3 dtex), combed cotton, carded cotton, and open-end cotton, in two different pile lengths of 0.7 and 1.0 mm and two different twist levels of 700 and 850 T/m. The results indicate that pile material types, pile lengths, and twist levels have significant effects on the boiling shrinkage of chenille yarns.

In this study, forty-eight different chenille yarns are produced on a chenille machine using a range of material types, twists, and gauges. In the first group, 4 Nm count chenille yarns are produced with six different pile materials, two different twists, and two different gauges. In the second group, 6 Nm count chenille yarns are produced with the same machine and material parameters. In order to measure the performance of chenille yarns, their abrasion resistance is measured with a chenille yarn abrasion device, and the abrasion resistance of upholstery fabrics made from these yarns used as filling is measured with a Martindale wear and abrasion tester. The results of pile loss are evaluated according to material type, twist, and pile length of the chenille yams. Clearly, there is an improvement in abrasion resistance with increasing twist, gauge (pile length), and the use of natural fibers as pile materials, which may be due to increasing frictional behavior between the pile and lock yarns.