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This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50- $\Omega $ load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50- $\Omega $ load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50- $\Omega $ load connection.

International audience; In this article, we leverage the power of machine learning algorithms to propose a test methodology for millimeter-wave (mm-wave) integrated circuits. The proposed test strategy is based on identifying the main process degradation mechanisms in a particular device under test (DUT) and then designing dedicated process monitor circuits to characterize this degradation and infer the DUT performance. The resulting process monitors do not load or couple to any of the DUT nodes, and the methodology can be adapted to any mm-wave device without complex codesign. The proposed test methodology is illustrated on a set of 21 fabricated samples of a 65-GHz PA designed in STMicroelectronics 55-nm CMOS technology.

International audience; A non-closed-form general mathematical model for CMOS distributed amplifier (DA) for broadband applications is presented. Contrary to the artificial transmission line (TL) assumption made in the conventional analytical models, the proposed model treats the DA as a discrete set of cells connected together, and hence considers propagation and mismatch between inter-cells. This approach provides designers with a much more accurate first sizing of the DA compared to conventional ways and, as a result, leads to a reduced design time and complexity. The model enables both quantitative and qualitative analysis of a DA, for the purpose of aiding the designers in predicting the relations between DA performance and its multi-design parameters, especially in the context of non-uniform designs. In addition, it is well suited to Computer-Automated Design (CAutoD), to help in achieving designs having a given set of performance goals. The validation of the model is demonstrated on two designs, by a comparison with simulations done in Keysight's ADS tool and using STMicroelectronics' 55-nm SiGe BiCMOS design kit. First design is inspired from an already published non-uniform DA design while second one proposes a 100-GHz bandwidth CMOS uniform DA with 8 dB of power gain, after using it in a CAutoD process.

International audience; This paper presents a sample & hold pulse envelope synthesis method and shows that only 5 (resp. 7) samples are necessary to respect the sidelobes rejection in adjacent channels of 18dB (resp. 20dB) required by the IEEE 802.15.4 (resp. 802.15.6) standard if a sample & hold Gaussian envelope is used. These required numbers of samples, which enable complexity reduction of IR-UWB emitters for IEEE standards, are validated using measurement results of a pulse synthesizer presented in this paper since a sidelobes rejection in adjacent channels of 21.8dB (resp. 21.4dB) is obtained when transmitting in the mandatory low band of the IEEE 802.15.4 (resp. 802.15.6) standard.

International audience; In the framework of circuits for 5G, this paper presents an innovative power efficient method to design cascaded distributed amplifiers. Validation is achieved with a 55-nm CMOS technology by ST -Microelectronics developed for the mm-wave range. Several rules are specified for analysis and design of an optimum structure, making the part between the number of trans conductances to be distributed and the number of distributed stages to be cascaded. Attention is also paid to the trade-off between power consumption and tunability. The Cadence Virtuoso tool is used to simulate the design which shows a targeted gain of 20 dB±0.8 dB over a bandwidth of 120 GHz with a power consumption of 174mW and an estimated area of 0.3 mm 2 .

The purpose of this paper is to study the complexity of the Harmonic Rejection N-Path Mixer HRNPM based receivers. In this framework, a HR-NPM architecture has been discussed based on the π-delayed driving signals. The harmonic rejection and the system complexity have been improved with this new architecture such that the Harmonic rejection achieved by this structure is the same of the conventional HR-2NPM and the system complexity has been reduced by half, where as the number of the gain stages and the switches has been reduced. In this context, a 5-path mixer is thus proposed. It allows rejecting up to the 8th harmonic with only 2 differential gain stages by appropriately implementing the switches whereas only the 6th harmonic would be rejected with conventional HR-8PM topologies having 3 amplifier stages. Our structure shows high resilience to clocks overlapping effects.

International audience; In this paper, an innovative millimeter-wave (mm-wave) through-load switch for in-situ reflectometers and on-wafer calibration is proposed. This two-port device can switch between two states: (i) a through connection or (ii) a 50 Ω load for both of its ports. The through-load switch is composed of a 3-dB directional coupler and two nMOS transistors controlled through a biasing voltage applied to their gate. Measurement results of a 120-GHz 3-dB directional coupler are provided up to 145 GHz together with EM simulations and circuit-level simulations up to 220 GHz of the through-load switch. A wide bandwidth is obtained, from 73 GHz to 179 GHz, with limited insertion loss of 2 dB.

This paper presents the design of a voltage controlled Standing-Wave Oscillator for applications in the E-band. A high quality factor tuneable Slow-wave Coplanar Stripline is used for the resonator. Varactors are distributed along the transmission line to mitigate the effect of their low Q-factor on the losses of the resonator. The Slow-wave Coplanar Stripline is asymmetrically sized to maximise the tuning range. The VCO achieves a measured phase noise of −114.9dBc at 80 GHz with 15mW power consumption and 3.3% continuous frequency tuning range.

International audience; This paper focuses on the design of high-performance Coupled Slow-wave CoPlanar Waveguide (CS-CPW) in CMOS technologies for the mm-wave frequency bands. First, the theory as well as the electrical model of the CS-CPW are presented. Next, the analytical approach for the calculation of the model parameters is discussed. Then, by using the developed model, two millimeter-wave backward directional 3-dB couplers are designed in a Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) 55-nm technology for 120 and 185-GHz operation, respectively. Simulation and experimental results demonstrate that the use of the CS-CPW concept leads to state-of-the-art performance, with a good agreement between the analytical model, electromagnetic simulations and measurement results.

International audience; The complexity of harmonic rejection N-path mixer based receivers is studied in this paper. A solution to improve harmonic rejection without increasing the complexity is presented and compared with conventional LNA-first receivers. This solution is based on π-delayed driving signals that enable a N-path mixer to present the same harmonic rejection than its 2N-path counterparts while reducing by 2 the frequency of operation and showing a reduced number of differential gain stages and switches. A 5-path mixer is thus proposed. It allows rejecting up to the 8 th harmonic with only 3 differential gain stages whereas only the 6 th harmonic would be rejected with conventional topologies having the same number of amplifier stages.

Integrated millimeter-wave (mm-wave) circuits fabricated in current nanometric processes are especially sensitive to process variations. This issue produces shifts in the circuit performance that may significantly reduce the fabrication yield. In this line, per-die characterization and trimming are usually required for mm-wave integrated circuits, but this is an expensive and time-consuming task to be performed at the production line. Embedded calibration for mm-wave circuits is an appealing alternative to enhance yield that may overcome some of these issues. In this work we present a two-stage 60 GHz power amplifier (PA), designed in STMicroelectronics 55 nm CMOS technology, that features a one-shot calibration procedure for process variation compensation based on non-intrusive process monitors. We present the design of a tuning knob based on variable decoupling cells which have been implemented within the PA for calibration purposes. The proposed one-shot calibration procedure reads the output of the embedded process monitors and then relies on a machine learning regression model to find the best configuration of the tuning knobs for optimizing the performance of the circuit and enhance fabrication yield.

A gm/ID based methodology is detailed in this paper in order to help the designers to determine the optimum size of a capacitive feedback LNA by considering the design topology, the specifications to reach and the technology characteristics. Thanks to this methodology, the gm/ID is maximized to minimize the power consumption under design constraints which are the voltage gain, the NF and the input inductor (input Q-factor set). To illustrate this methodology, some capacitve feedback LNAs have been designed with different voltage gain requirements in 28nm FDSOI technology for 2.4GHz applications. Based on the initial parameters obtained following the different steps, three LNAs have been designed and simulated. The post-layout simulation results exhibit very good performances in terms of power consumption, linearity IIP3, bandwith BW and noise figure NF for the three given voltage gains (15dB, 18dB and 20dB). The achieved performances are quantified by high values of a well known FoM.

International audience; A study of the non-inverting amplifier based on a two stages CMOS unbuffered current-feedback-operational-amplifier (UCF0A) is proposed in this paper. Using a small-signal equivalent circuit (macro-model) of the non-inverting amplifier, a theoretical explanation of the closed loop gain is given. The opamp phase margin and its bandwidth have been estimated from the quality factor Q of resonance and using a novel description of the UCF0A input stage called Operational Transconductance Conveyor (OTC). The OTC description can be viewed as an extension of type II second generation current conveyors. Based on the fundamental parameters of the proposed OTC, a theoretical approach given in this paper explains how to evaluate precisely the value of the UCFOA compensation capacitance. PSPICE was used to simulate both the theoretical macro-model and the CMOS configuration from a 0.35m typical BSIM3V3 transistor models.

This paper presents a $g_{n}\sqrt {}I_{D}$ based design methodology for a capacitive feedback LNA topology. The proposed method gives the optimal value of $g_{n}\sqrt {}I_{D}$ to achieve the required performances (Gain and Noise Figure) while ensuring the minimum consumption. Moreover, it makes possible the sizing of all the components of the structure with a degree of freedom for the inductance value needed for the input power matching. This methodology is illustrated through the design of a $2. 4\mathrm {G}\mathrm {H}\mathrm {z}$ LNA in the $28\mathrm {n}\mathrm {m}$ FDSOI technology from ST-Microelectronics.

The functional test of millimeter-wave (mm-wave) circuitry in the production line is a challenging task that requires costly dedicated test equipment and long test times. Machine learning indirect test offers an appealing alternative to standard mm-wave functional test by replacing the direct measurement of the circuit performances by a set of indirect measurements, usually called signatures. Machine learning regression algorithms are then used to map signatures and performances. In this work, we present a generic and automated methodology for finding an appropriate set of indirect measurements and assisting the designer with the necessary Design-for-Test circuit modifications. In order to avoid complex design modifications of mm-wave circuitry, the proposed strategy is targeted at generating a set of non-intrusive indirect measurements using process variation sensors not connected to the Device Under Test (DUT). The proposed methodology is demonstrated on a 60 GHz Power Amplifier designed in STMicroelectronics 55 nm BiCMOS technology.

International audience; Beam-forming techniques using phased arrays are one of the most promising solutions for the practical imple- mentation of future high-data-rate point-to-point communication protocols. The functionality of phased arrays is based on the use of phase shifters that should provide an accurate and controllable phase difference between the different paths of the array. However, the integration of phase shifters in current nanometric technologies is prone to imperfections that may affect the intended phase shift and degrade the performance of the antenna array. This requires extensive testing and calibration and represents a bottleneck in the production line of these system. In this work, we propose a simple Oscillation-Based Test technique that may be suitable for Built-In Self-Test applications of phase shifters. The technique is demonstrated on a Reflection-Type Phase Shifter implemented in a 55 nm BiCMOS technology. Elec- tromagnetic and electrical simulation results show the feasibility of the proposed technique.

This paper presents the design of a mm-wave VCO with high quality factor slow-wave coplanar stripline synthesized inductor. The objective is to show the advantage of using slow-wave coplanar stripline to improve the figure of merit. For that purpose, the proposed VCO is compared to its classical LC-tank VCO counterpart in the same technology. Both VCOs use same varactors and are designed for center frequency of 80 GHz in BiCMOS 55 nm technology. Due to high quality factor (≈38) of slow-wave coplanar stripline, the phase noise is 6 dB better and power consumption is 30% lower than classical LC-tank VCO. The slow-wave coplanar stripline based VCO also achieved 17% higher frequency tuning range. The measured phase noise is −112 dBc/Hz at 10 MHz offset for the proposed VCO with power consumption of 6.3 mW and output power of −3 dBm.

This paper presents the design of a voltage controlled oscillator at mm-wave frequencies in the 22-nm Fully Depleted Silicon On Insulator technology from GlobalFoundries (22FDX). The low-quality factor inductance was replaced by a high-quality factor slow-wave transmission line. Including the output buffers, the oscillation frequency is centred at 80 GHz, with as a low-power consumption of 6.7 mW, an output power of −15.5 dBm and a phase noise of −104.7 dBc/Hz at 10 MHz offset.

International audience; A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2-8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (< 1 ns) and an average sensitivity of -92 dBm for a 10(-3) BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 A mu W. Simulation results of the fully integrated self-duty-cycled 7.2-8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 A mu W and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).

This paper presents a high-rate IR-UWB transceiver chipset implemented in a 130-nm CMOS technology for WBAN and biomedical applications in the 3.1–4.9 GHz band. The transmitter is based on a pulse synthesizer and an analytical up-converted Gaussian pulse is used to predict its settings. Its measured peak-to-peak output voltage is equal to $0.9~V_{\mathrm{ pp}}$ on a 100 $\Omega $ load for a central frequency of 4 GHz, and a supply voltage of 1.2 V, which gives an emitted energy per pulse of 0.64 pJ. The receiver is a non-coherent architecture based on an LNA followed by a peak-voltage detector. A BER of 10−3 is measured for a 3.1–4.9 GHz input peak-to-peak pulse amplitude of 1.1 mV, which corresponds to a sensitivity of −85.8 dBm at 1 Mb/s and gives a communication range estimated to 1.9 m.

An ultra low power and low voltage down conversion mixer is presented in this paper for the frequency band of 1.8-2.4GHz. Designed in 0.18 µ m CMOS technology, the double balanced proposed mixer is composed by two cascaded stages. The first one is based on cross coupled capacitors technique in current reused topology providing a high voltage gain, while the second one employs a current reused transducer coupled to LO driven inverters to perform the down conversion. All the devices operate on moderate inversion for better trade-off between gain, linearity, and low power consumption. The post layout simulation shows a 23dB of voltage gain conversion, an IIP3 of -2dBm, with 300 µ W of power consumption under 0.9V voltage supply.

This paper presents some techniques to synthesize pulses in the context of IR-UWB. Pulse synthesizers are good candidates when different kinds of pulses are needed to comply with different standards or when the shape of the pulses needs to be modified. Two different approaches are described here. Voltage Controlled Delay Line (VCDL) based pulses are first described. For this family, two kinds of combiners are presented: differential pairs based and H-bridge based. The second one achieves a larger output dynamic but is limited by the use of the VCDL. A second type of H-bridge based synthesizer using VCO is presented. Using both a VCO and a H-Bridge offers the largest synthesis capabilities since it allows large voltage pulses to be synthesized and the pulse duration is not limited. All proposed architectures have been implemented and their measured performances are given for comparison.

19th Bi-Annual French National Microwave Days (JNM), Bordeaux Inst Technol, Bordeaux, FRANCE, JUN 02-05, 2015; International audience; This paper presents the design of a fully integrated ultra-low-power Ultra Wide Band (UWB) pulse generator. The circuit is designed and optimized for low rate and localization applications. This UWB transmitter is based on the impulse response filter method in order to achieve high energy sub-nanosecond pulses. The circuit has been integrated in a ST-Microelectronics CMOS 0.13 mu m technology with a supply voltage of 1.2 V on a die area of 0.56 mm(2). A power manager is used to reduce the power leakages to 3.91 mu W which gives a power consumption of 3.98 Mw at 10 kb/s. The measured dynamic energy consumed per pulse is 68 pJ and the measured energy of the emitted pulse is 2.15 pJ.

International audience; In this paper, we propose a low-power technique, called RF power gating, which consists in varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on the bit error rate (BER) performances is studied for a basic estimator in the specific case of minimum-shift keying signaling. A system-level energy model is also derived and discussed to estimate precisely the power reduction based on the characteristics and the power consumption of each block. This model allows highlighting the different contributors of the power reduction. The BER results and the energy model are finally merged to determine the best ATR meeting the design constraints. Applying this technique to the IEEE 802.15.4 standard, this paper shows that an ATR of 20% is a good tradeoff to meet the packet error rate constraint while maximizing the energy reduction ratio. Using typical block power consumptions, an energy reduction ratio around 20% can be reached. Even better energy reduction ratios (~60%) are also achievable when most of the blocks are power-gated.

This paper presents the design of a fully integrated ultra-wideband (UWB) pulse generator for the Federal Communications Commission (FCC) 3.1-10.6-GHz band. This generator is reserved for medium rate applications and achieves pulses for an on-off keying (OOK) modulation, pulse position modulation, or pulse interval modulation. This UWB transmitter is based on the impulse response filter method, which uses an edge combiner in order to excite an integrated bandpass filter. The circuit has been integrated in an ST-Microelectronics CMOS 0.13-?m technology with 1.2-V supply voltage and the die size is 0.54 mm2. The pulse generator power consumption is 9 pJ per pulse and achieves a peak to peak magnitude of 1.42 V. The pulse is FCC compliant and the generator can be used with a rate up to 38 Mbs-1 with an OOK modulation. Based on the FCC power spectral density limitation, a sizing method is also presented.

A new operational transconductance amplifier (OTA) builds with CMOS inverters only is proposed in this paper. Simulations with typical BSIM3V3 parameters of a 0.35 μm CMOS process have shown a 3.56 GHz gain-bandwidth product under 2.5 V supply voltage. The corresponding total harmonic distortion is equal to 0.46% for 2 V peak---peak differential output voltage. At the same supply voltage, the circuit can provided at each output a voltage swing of 2.25 V peak---peak. From VDD = 2 V to VDD = 2.5 V the differential transconductance varies from 72 to 108.4 μ??1. The corresponding common mode rejection ratio and the total power consumption are always lower than ?31 dBc and 800 μW, respectively. Typical application of a biquad filter is proposed to illustrate the circuit capabilities.

Healthcare applications requirements are presented in this paper and a state-of-the-art analysis shows that Impulse Radio Ultra-WideBand (IR-UWB) is particularly suitable in terms of energy efficiency for this type of short range communications for which different data rates are needed. Power saving strategies for emitters and receivers are then discussed and three examples of implementations are presented with their measurement results. The first is a versatile transmitter with tunable bandwidth which exhibits 0.9Vpp pulses and a power consumption of at least 11.03mW at 50Mbps. The second is a 3.1-10.6GHz transmitter with a power management scheme implemented on-chip which exhibits 2Vpp pulses and a power consumption of 7.3uW at 100kbps and 3.4mW at 100Mbps. The last is a non-coherent 3-5GHz receiver with -89dBm sensitivity at 100kbps and 144pJ/bit energy consumption when used in a power gated 100Mbps burst mode.

In this paper, an implementation of both interpolation and synchronization modules designed for RF receiver using power-gated ADC (PG-ADC) is presented. These modules allow lower bit error rates when demodulating non-uniformly sampled minimum-shift keying (MSK) signal. The proposed architectures are synthesized using CMOS 90 nm technology and are shown to have small occupied area (≈0.05 mm2) and low power consumption (tens to hundreds of µW). The results are detailed for several input data rates and interpolation factors.

An ultra-wideband Voltage Controlled Oscillator (VCO) is presented in this paper. The circuit achieves fast startups and stops which allow wideband pulses to be generated. In addition, the VCO allows bipolar modulations as Binary Phase Shift Keying to be implemented without the need of a shaping circuit as a mixer. The proposed VCO has been integrated on a silicon area of 0.003mm2 in a 65nm CMOS technology operating with a supply voltage of 1.2V. The oscillator output provides large differential oscillations from 2.6GHz to 12.3GHz. Measurement has demonstrated the frequency agility of the proposed VCO which covers the mandatory channels of the low (resp. high) bands centered on 4492.8MHz (resp. 7987.2MHz) defined by the IEEE 802.15.4 standard. The VCO power consumption is about 3.2mW/GHz. By using Current Mode Logic (CML) gates, the power consumption can be reduced to 3.84uW only when the VCO is not running (switch off).

A compact reconfigurable CMOS low-noise amplifier (LNA) is presented for applications in DCS1800, UMTS, WLAN-b/g and Bluetooth standards. The proposed LNA features first a current reuse shunt-feedback amplifier for wideband input matching, low-noise figure and small area. Secondly, a cascode amplifier with a tunable active LC resonator is added for high gain and continuous tuning of bands. Fabricated in a 0.13 μm CMOS process, the measured results show >20 dB power gain

International audience

This work presents a novel fast switching low power low noise amplifier (LNA) for 6–10 GHz ultra wide band applications using 0.13μm CMOS process from STMicroelectronics. The LNA operates at 1.2V. It achieves a high differential voltage gain about 46 dB with 4.4dB noise figure and a power consumption of 24mW. Fast on and off power switching is achieved by using differential amplifiers with DC coupled eliminating the use of large capacitors that leads to long charging time constants. The output voltage is settled in 1.5 ns when the LNA is switched on and off. The circuit consumes only 32.4 μW of dc power when duty-cycled@100kbps allowing reducing the power consumption.

IMNP Marseille; International audience; This paper presents the design of a fully integrated pulse generator which allows BPSK modulation to be implemented. This emitter is based on the response filter architecture and has been integrated in a 130 nm CMOS technology with a 1.2 V supply voltage on a silicon area of 2.88 mm 2 . The bandwidth at -10 dB is about 1.8 GHz around 3.52 GHz. The output dynamic voltage is equal to 1.72 V peak to peak on a 100 Ω differential load which gives an energy of 1.93 pJ for the twice bipolar generated pulses and demonstrates the pulse generator capability to be used for bipolar modulations.

The design of an UWB pulse generator is presented. The pulse generator is based on an elementary pulse combination technique which enables the emitted pulse to be precisely shaped. This technique is implemented with no inductor or passive network and can be used to ensure regulation compliance. This generator has been fully integrated in a 0.13 μm CMOS standard technology. Its area is 0.06mm2 only and it can be programmed to synthesize different pulse shapes. For FCC compliant pulse shapes, the maximum measured 10dB bandwidth is 3.5GHz, and the maximum peak to peak magnitude is 220mV. The measured maximal power consumption is 87.6mW at 800MHz Pulse Repetition Frequency (PRF).

A Digital CMOS BPSK modulator is presented in this paper. PSPICE simulation results of the proposed modulator are presented using BSIM3v3 transistors process parameter of the TSMC-0.18μm 1.8V CMOS technology. Between 1.6V to 1.8V supply voltage, the carrier frequency of the proposed modulator is scalable between 2.3GHz and 2.6GHz. Due to its symmetry, the proposed digital BSK modulator is fully differential.

In this paper, a low power and low cost ultra wideband impulse radio transmitter is presented. The transmitter includes a pulse generator integrated in a 0.13- $\mu{\rm m}$ standard CMOS technology and an antenna printed on the chip carrier. The board is manufactured with Roger 4003 laminate substrate and has a total area of 50 mm $\times\,$ 18 mm. The transmitter provides 1.4 V peak to peak Federal Communications Commission compliant pulses at antenna input for data rates up to 36 Mb/s in an on–off keying modulation scheme. The transmitter's power consumption is 12 mW at 1.2-GHz pulse repetition frequency and the energy consumption is 10 pJ per pulse. A 365-mV peak voltage emitted pulse is measured in an anechoic room at 0.8 m range with a receiver, including a horn antenna (8.3 dBi), a LNA (32 dB), and a 12-GHz real time oscilloscope.

This paper presents a reconfigurable inductor-less CMOS low noise amplifier (LNA) for multi-standard wireless applications. The LNA is designed to address PCS1900, UMTS, WLANb/g and Bluetooth frequency bands. The LNA is based on two cascaded stages. The first stage is a resistive feedback amplifier which achieves a wideband matching in order to address the different application frequency bands while performing a low noise figure. The second stage is a cascode amplifier with an active output LC resonator in order to select the desired bandwidth while achieving high gain and low surface area. The proposed multi-standard LNA, implemented in a 0.13µm CMOS technology achieves more than 26dB gain from 1.8 to 2.4GHz for a noise figure less than 3.4dB. The input and output return losses S11 and S22 are lower than −12dB and −16dB respectively. The LNA consumes 9.6 mA from 1.2V supply voltage and occupies a chip area of 0.165mm2 including pads.

The design of a remotely UHF powered UWB transmitter is presented in 0.13µm CMOS standard process. Power harvesting unit is based on a Dickson voltage multiplier and UWB pulse generator uses filtered combined edge method. Multi-Vt technique and CMOS logic allows pulse generator power consumption between two consecutive pulses to be reduced enough to be remotely powered. It achieves FCC compliant pulses having 1.82Vpp and a PRF of 15kHz at 10m thanks to the power harvesting unit.

This paper focuses on the frequency-down-conversion realized with a proposed Mixer topology using 4 CMOS inverters only. From simulation and using typical 0.35µm CMOS process parameters, the proposed Mixer exhibits at 900MHz under 2.5 supply voltage, the following performances: a 16.8dB conversion gain, a 23dBc-IM3 with 200mVpeak-to-peak input sinusoidal waves. The corresponding IIP3 is 10dBm for a total power consumption of 1.4mW.

The design and the implementation of Ultra-wide-band (UWB) CMOS LC filter LNA for Ultra Wide Band carrier less Impulse Radio receivers is presented. Architectures for both single ended and differential ended LNA are proposed for small fractional bandwidths such as the ECC frequency band and for large fractional bandwidths such as FCC frequency band. Simple guidelines to achieve large voltage gain and low noise figure are given. The implementation in standard CMOS technologies in the context of integrated receivers is discussed and simple layout rules allowing reliable designs are proposed. Several LNA prototypes for different fractional bandwidths have been fabricated in a 0.13 μm CMOS technology. Measurement results agree well with the simulations.

A low power CMOS energy detector for 3.1–10.6 GHz non-coherent impulse-radio UWB receivers is implemented in a 0.13 µm CMOS process. The detector architecture is based on a squarer circuit realized with MOS transistors biased in the sub-threshold region. The squared signal is integrated using a low pass amplifier that allows the receiver gain to be optimized. A comparator with a tunable threshold is then used as a decision circuit. Experimental results show that a BER of 10− is achieved for a peak-to-peak voltage of 140 mV at the detector input at 200 Mb/s data rate. Assuming that the detector is driven by a LNA of gain 22 dB, leads to a receiver sensitivity of −45 dBm. The receiver dissipates only 25 mW, corresponding to an energy efficiency of 0.13 nJ/bit and the chip occupies 0.7 mm2.

The design of a fully tunable pulse generator using only logic cells is presented and simulated with 0.13µm standard CMOS process. The generator is based on the elementary pulse combination and can synthesize different UWB pulse shapes. The generator uses logic gates to achieve the elementary pulses and a H-bridge to make the combination which leads to a zero DC power consumption. To achieve FCC compliant pulse having 2V PP magnitude the generator consumes 140 pJ by pulse using 1.2V supply voltage.

The design of an UWB pulse generator is presented in the context of low cost applications. The pulse generator is fully integrated in a 0.13 μm CMOS technology and achieves 1Vpp magnitude pulses with only 2.25pJ of energy consumed by pulse and 1.2V voltage supply. The generation method used in this design is well suited for packaged IC using wire bond interconnections. Tow methods of interconnection are presented. It is shown that a co-design of the generator with the package transition can preserve the signal integrity while increasing the pulse magnitude up to 1.4Vpp with the same power budget.

The design of a fully integrated CMOS low noise amplifiers (LNA) for ultra-wide-band (UWB) integrated receivers is presented. An original LC input matching cell architecture enables fractional bandwidths of about 25%, with practical values, that match the new ECC 6-8.5-GHz UWB frequency band. An associated design method which allows low noise figure and high voltage gain is also presented. Measurements results on an LNA prototype fabricated in a 0.13-mum standard CMOS process show average voltage gain and noise figure of 29.5 and 4.5 dB, respectively.

We present in this paper some design rules to improve the signal integrity (SI) of a package transition. The design rules are based on standard low-pass (LP) filter synthesis methodology. This methodology uses the modeling of the package transition by a pi network and is valid as long as the through phase shift of the package transition remains sufficiently small. Based on this pi network approximation, it is possible to add external distributed elements at the package carrier level and lumped elements at the DIE level to build an equivalent low-pass ladder filter. This approach improves significantly the signal integrity properties of the package transition without modifying the package. In some cases the frequency bandwidth for which the return loss (RL) remains higher than 20 dB can be doubled by using this method.

The design of a traveling-wave amplifier (TWA) in 0.13-mum standard CMOS technology is presented. It is designed to maximize the gain-bandwidth product (GBP). An asymmetric cascode, coplanar waveguide (CPW), and loss compensation technique enables maximization of the TWA GBP. Design and modeling of 90-Omega CPW used to synthesize inductors of the TWA lines is presented. Simulations with a design kit and developed models for CPW show a 52-GHz bandwidth with a maximum power gain of 8.5 dB at 10 GHz for a 135-mW power consumption. Measurements up to 40 GHz confirm these results.

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 µm CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6–10 GHz frequency band with a power consumption of 14 mW.

In this paper we propose a design methodology to synthesize a band pass (BP) filter while embedding a package transition using wire bound attach process. The BP filter uses quarter wave coplanar line at the PCB level, the package transition and passive elements on DIE. The BP filter is designed for a low noise amplifier (LNA) receiver in the ECC- UWB band (6-8,5 GHz).

In this paper we analyze a characterization test plan of a printed circuit board (PCB) to a flip chip DIE transition trough a ceramic ball grid array (CBGA) package. From finite element method (FEM) simulation results, we propose a testing methodology to extract the wide band RF scattering S parameters of the PCB to the DIE transition. The test plan includes a deembedding short open line (SOL) technique, and a trough reflect line (TRL) calibration on PCB.

A versatile 5th order low-cost GM-C low-pass-filter for a Zero-IF base-band demodulation scheme is presented in this paper. The circuit is designed for a low-power 2.45GHz direct-conversion receiver based on frequency shift keying (FSK) modulation with a 2MHz corner frequency to provide rejection of the adjacent channels. Corner frequency of the proposed filter can be easily controlled from a DC bias current source. The circuit has been simulated under 2.5V using the 0.28?m standard CMOS process technology. The total output noise density is equal to 47nVrms at 2MHz. The corresponding total harmonic distortion is lower than 0.3% when a 2MHz-20mV peak-to-peak input sinusoidal voltage is applied. At the same simulation conditions and up to 8MHz, the circuit exhibits a frequency-rejected higher than 28dBc. The filter total silicon area is 100?m×100?m and the total current consumption is 180?A under 2.5V supply voltage.