1. Radiation Tolerant SRAM Cell Design in 65nm Technology
- Author
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Shuting Shi, Li Chen, Lixiang Li, Xue Wu, Haonan Tian, and JianAn Wang
- Subjects
business.industry ,Computer science ,020208 electrical & electronic engineering ,Sram cell ,Schematic ,Dice ,02 engineering and technology ,Radiation ,Chip ,020202 computer hardware & architecture ,CMOS ,0202 electrical engineering, electronic engineering, information engineering ,Overhead (computing) ,Static random-access memory ,Electrical and Electronic Engineering ,business ,Computer hardware - Abstract
In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings.
- Published
- 2021