Search

The right ventricular assessment is crucial to heart disease diagnosis. Unfortunately, its segmentation is quite challenging due to its intricate shape, ill‐defined thin edges, large variability among patients, and pathologies. Besides, it is a very laborious and time‐consuming task to be done manually. Therefore, automated segmentation techniques are very suitable to reduce the strain on the expert. Here, it is attempted to review the taxonomy of the current RV segmentation approaches adopted to handle the afore‐mentioned issues. Enhanced by our expert's interpretation, the results of over forty research papers were evaluated based on several metrics such as the dice metric and the Hausdorff distance. Synthetic tables and charts were also used to discuss the reviewed approaches. The following study shows that none of the existing methods has proved accurate enough to meet all the RV challenging issues. Many misestimated results were reported for several cases. Eventually, global guidance is outlined, which supports combining different methods to enhance the expected results during the MRI short‐axis slice processing.

The present work develops a novel hybrid method for ocular and muscular artifact removal from electroencephalography (EEG) signals, EFICA-TQWT. It is a combination of efficient fast independent component analysis (EFICA) method with the tunable Q-factor wavelet transform (TQWT). The main contribution of this paper is to apply the 3D interpolation method in the filtering system. Three EEG datasets are used in this work, two healthy and one epileptic. The choice of subjects for each dataset is made with the help of an expert in physiology. The selection criterion adopted is the presence of muscular and ocular artifacts in the processed recordings. First, a noisy channel automatic classification is performed by the support vector machine (SVM) with radial basis function in order to delete the signal(s) corresponding to the noisiest channel(s) from each EEG recording. The results of the automatic classification by the SVM were compared with those found by the expert’s classification. An accuracy of 97.45%, a sensitivity of 86.66% and a 100% specificity are provided by the SVM classification. The hybrid method of artifact removal will be applied on the rest of the EEG channels of international 10/20 system for each subject. Then, a reconstruction of the eliminated channel signal(s) will be performed in order to obtain a well-filtered signal. The proposed filtering process is evaluated by calculating the mean squared error (MSE) and the signal to noise ratio (SNR). Both for the healthy and pathological EEG datasets, a comparative study of the proposed method (EFICA-TQWT) and other filtering techniques (Fast-ICA, DWT, TQWT and EFICA) is generated. The EFICA-TQWT method gave the best results with a minimum of MSE and a maximum of SNR, more particularly in the case of the application of the 3D interpolation method. Besides, in order to optimize the computing time of the proposed system, a parallel implementation of this filtering system is developed based on graphical processing units using compute unified device architecture.

In this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the processing units called neuroprocessors (NPs) which define the SSOM architecture. The NP modules have an innovative architecture compared to those proposed in the literature. Indeed, each NP performs three different tasks without requiring additional external modules. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on an FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in the recent literature.

In the era of the Internet of Things (IoT) and Big Data (BD), a significant amount of data is permanently generated every day. The data size of collected data streams is now reaching zetta bytes (i.e., 1021), and their processing and analysis becomes more and more challenging especially in embedded systems, where the overall goal is to maximize performance per watt, while meeting real-time requirements and trying to keep the overall power consumption in the very limited power budgets. The collected data are often reduced by means of clustering, vector quantization or compression before their further processing. The unsupervised learning techniques such as Self-Organizing Maps (SOMs) not needing any prior knowledge of processed data are perfect candidates for this task. However, real-time vector quantization with SOMs requires high performances and dynamic online configurability. The software counterparts of SOMs are highly flexible with limited performances per watt whereas the hardware SOMs generally lack of flexibility. In this paper, a novel scalable, dynamic and growing hardware self-organizing map (SOM) is presented. The presented hardware SOM architecture is dynamically configurable and adaptable in terms of neurons, map size and vector dimension depending on the application-specific needs. The proposed architecture is validated on different map sizes (up to 16×16) with different vector widths applied for real-time color quantization and pattern distribution recognition.

The LoRaWAN technology is today the object of great interest in the Internet of Things context. It defines a simple network architecture offering a wide-area wireless coverage for low rate IoT applications with low power consumption for devices. The LoRaWan class A is designed for sensor networks with a focus on the uplink. LoRaWan defines an optional MAC operation, Class B, that provides the network server with the opportunities to initiate a downlink, which can be a real solution for actuators focus network. Today, Performances of Class B are not quantified and compared to default LoRaWAN class. In this paper, we propose an evaluation of Class B performance. We offer a set of realistic evaluation scenarios based on an NS-3 simulation module that we have developed for this purpose. Results show that Class B reduces the delivery delay of downlink traffic in comparison to Class A. Class B operation significantly reduces the percentage of packet loss for downlink traffic even in congested contexts. We conclude that a trade off should be made between having low access delay or packet loss. Both the NS-3 module and data are released as an open-source to the research community.

Several leading-edge applications such as pathology detection, biometric identification, and face recognition are based mainly on blob and line detection. To address this problem, Eigen value computing has been commonly employed due to its accuracy and robustness. However, Eigen value computing requires a raised computational processing, intensive memory data access, and data overlapping, which involve higher execution times. To overcome these limitations, we propose in this paper a new parallel strategy to implement Eigen value computing using a graphics processing unit (GPU). Our contributions are (1) to optimize instruction scheduling to reduce the computation time, (2) to efficiently partition processing into blocks to increase the occupancy of streaming multiprocessors, (3) to provide efficient input data splitting on shared memory to benefit from its lower access time, and (4) to propose new data management of shared memory to avoid access memory conflict and reduce memory bank accesses. Experimental results show that our proposed GPU parallel strategy for Eigen value computing achieves speedups of 27 compared with a multithreaded implementation, of 16 compared with a predefined function in the OpenCV library, and of eight compared with a predefined function in the Cublas library, all of which are performed into a quad core multi-central-processing unit platform. Next, our parallel strategy is evaluated through an Eigen value-based method for retinal thick vessel segmentation, which is essential for detecting ocular pathologies. Eigen value computing is executed in 0.017 s when using Structured Analysis of the Retina database images. Accordingly, we achieved real-time thick retinal vessel segmentation with an average execution time of about 0.039 s.

International audience; The current challenge for image treatment, targeting the heart ventricles (LV and RV), consists on ensuring an accurate automatic segmentation aiming to identify the myocardial contours. In this paper we propose an automatic watershed-based segmentation of the left ventricle (LV)based on topology, geometry and brightness priors. We attempted to demonstrate the accuracy of our proposed approach by comparing it with other manual segmentations carried out by two clinical experts, on 20 patients. In the aim of obtaining an accurate 3D reconstruction, we propose the volumetric object reconstruction method using The Visualization Toolkit VTK .Furthermore, the 3D+t assessment is used for the examination of the dynamic behavior of the LV to reveal regions of myocardial dysfunction.

International audience; Watershed Transform is a widely used image segmentation technique that is known to be very data-intensive and time-consuming. The M-border Kernel Algorithm computes watersheds in the framework of Edge Weighted Graphs and allows to preserve the topology of the initial map. Par-allelization represents an effective solution to accelerate it. However, this task remains challenging due to the nature of this technique. In this paper, we address this problem. We start by analyzing the Data Dependency Issues that this algorithm raises when dealing with parallel execution. With respect to that, we propose a parallelization strategy that opts for vertices scanning instead of edges scanning of the graph while preserving the thinning paradigm on which the M-border Kernel Algorithm is based. We show that this strategy overcomes the problem of the simultaneous lowering of two adjacent M-border edges that may occur when edges scan is used. The implementation of the proposed algorithm on a shared memory multicore architecture proves its effectiveness in terms of speedup. In fact, the experimental results show that a 2 Yosra Braham et al. speedup factor of 5.55 is achieved using 8 processors for 2048 × 2048 images over the performance of the sequential algorithm using a single processor on the same architecture. Furthermore, the gain in terms of execution time and thus speedup is guaranteed whatever is the size of images on which the algorithm is applied. In fact, a speedup factor of 5.55 is obtained for 2048 × 2048 images, 5.11 for 1024 × 1024 images and 4.45 for 512 × 512 images using 8 cores.

Due to their ability to reduce the size of high-dimensional input data, self-organizing maps (SOMs) can be employed as data quantizers. The widely used software implementations of SOM enjoy flexibility and adaptability, usually to the detriment of performances, which limits their use in real time applications. On the contrary, the hardware counterparts of SOMs exploit the inherent parallelism of hardware to boost the overall performances, but generally lack adaptability without considerable design efforts. To benefit from both, the flexibility of software and performances of hardware SOM implementations, unconventional design approaches of SOMs should be used. In this work, a scalable and adaptable hardware implementation of a SOM network is presented. The proposed architecture allows to dynamically extend the SOM operation from a smaller to a larger map only by (re-)configuring the parameters of each neuron. The gained scalability is obtained by decoupling the computation layer composed of neurons, from the communication one, used to provide data exchange mechanisms between neurons. The proposed SOM architecture is also validated through simulation on variable-sized SOM networks applied to image compression.

A novel approach is proposed for medical analysis and clinical decision support of the Electrocardiogram (ECG) signals based on the deterministic finite automata (DFA) with the addition of some requirements. This paper proves regular grammar is effective in the extraction of QRS complex and interpretation of ECG signals. The DFA will be used to represent a normalized QRS complex as a sequence of negative and positive peaks. A QRS is considered as a set of adjacent peaks that satisfy certain criteria of standard deviation and duration. The proposed method is applied on several kinds of ECG signals collected from the standard MIT-BIH arrhythmia database. Several metrics are calculated including QRS durations, RR distances and peak amplitudes. Furthermore, σRR and σQRS metrics were added to quantify RR distances regularity and QRS durations, respectively. Regular grammar with the addition of some requirements and deterministic automata proved functional for both biomedical signals and ECG signal diagnosis. The suggested method provided a sensitivity rate of 99.74% and the positive predictivity rate of 99.86%. The algorithm was compared to other works in the literature and the quality performance detection was compared with several algorithms tested and validated on the MIT-BIH database. A head-to-head comparison in terms of sensitivity and CPU runtime was provided with the wavelet method.

This study presents an architecture-optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low-power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors’ architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.

In this work, a scalable and adaptable hardware SOM architecture allowing to execute multiple applications in parallel is presented. The proposed architecture allows to use simultaneously multiple SOM structures with different parameters in order to satisfy multiple applications with different needs. The application switching is done within a clock cycle at the neuron’s level at run time only by analyzing the received input data. The proposed architecture was tested and validated in an image quantization experiment where 6 quantization applications with different parameters (from 6 × 6 to 15 × 15 SOMs with inputs varying from 3 to 12 elements) were performed simultaneously.

X-ray Coronary angiograms are intended to specify the global state of the artery system and therefore to detect and locate the zones of narrowing. Accurate coronary artery segmentation is a fundamental step in computer aided diagnosis of many diseases. In this paper, deep neural network based on U-Net architecture is proposed in order to improve the segmentation task for coronary images. In this context, various enhancement methods, like the adaptive histogram equalization and the multiscale technique with a Frangi filter are tested not only in normal conditions but also in the presence of noise to improve the system performance and to ensure its robustness against real conditions. Promising result are obtained and discussed for different performance criteria. This work will serve as a reference and motivation for researchers interested in the field of blood vessel segmentation by deep learning neural networks.

In this paper we present a new architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called Systolic-SOM (SSOM), is based on a generic formalism that exploits two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the neuroprocessors that define the SSOM architecture. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in recent literature.

The development of hardware platforms for artificial neural networks (ANN) has been hindered by the high consumption of power and hardware resources. In this paper, we present a methodology for ANN-optimized implementation, of a learning vector quantization (LVQ) type on a field-programmable gate array (FPGA) device. The aim was to provide an intelligent embedded system for real-time vigilance state classification of a subject from an analysis of the electroencephalogram signal. The present approach consists in applying the extension of the algorithm architecture adequacy (AAA) methodology with the arithmetic accuracy constraint, allowing the LVQ-optimized implementation on the FPGA. This extension improves the optimization phase of the AAA methodology by taking into account the operations wordlength required by applying and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. This LVQ implementation will allow a considerable gain of circuit resources, power and maximum frequency while respecting the time and accuracy constraints. To validate our approach, the LVQ implementation has been tried for several network topologies on two Virtex devices. The accuracy–success rate relation has been studied and reported.

In this work, a new method for removal of ocular and muscular artifacts from Multi-channel electroencephalogram (EEG) is presented in order to obtain a 3D filtered cerebral mapping images. First, a FastICA algorithm of Independent Component Analysis (ICA) is applied in combination with the tunable Q-factor wavelet transform (TQWT), FastICA-TQWT. Then, to show the robustness of this method, a comparison was made between the proposed FastICA-TQWT method and the classical one FastICA-DWT based on three criteria: Mean Squared Error (MSE), correlation coefficient and Signal Noise Ratio (SNR). The results showed that the FastICA-TQWT method gave the highest Signal Noise Ratio and correlation coefficient and the minimum Mean Squared Error. However, the FastICA-TQWT algorithm requires an extremely high computing power. Therefore, the second contribution of this paper is to provide an EEG signal treatment by implementing the hybrid FastICA-TQWT algorithm using a new computing technology designed for a high-performance computing, called Graphical Processing Units (GPUs) using the Compute Unified Device Architecture (CUDA) technology. The performance of the parallel approach running along the GPU was compared to a CPU implementation.

Heart rates have normal values ranging from 60 to 80 beats per minute (bpm) for adults. RR distances have normal durations between 0.75 and 1 second. The complexes QRS durations have normal durations of less than 0.1 second. However, heart rate and RR distances also depend on age (adult or child), the patient's status (rest or stress), sex (male or female) and the patient's conditions (healthy or pathological). Heart rates, RR distances and QRS durations are not sufficient to determine whether ECGs are normal or pathological. Recently, two novel metrics have been calculated to reflect the regularity of RR distances and the QRS complexes durations irrespective of the patient's age, sex and heart rate. In this paper, these novel parameters were tested and validated on the arrhythmia (MIT-BIH), Abdominal and Direct Fetal ECG (ADFECGDB) and BIDMC Congestive Heart Failure (CHFDB) databases.

This work applies a novel method called multiquadratic interpolation that represents a 3D brain activity following a spatiotemporal mode. It also develops other classical interpolation techniques (barycentric, spline), which are based on the calculation of the Euclidean distance between the estimated and measured electrodes. Then, it modifies these methods by substituting the Euclidean distance by the corresponding arc length. Starting from 19 real electrodes for generating the electroencephalogram (EEG) potential representations of healthy subjects having three different behavioral brain states, a 3D EEG mapping of 128 electrodes was obtained. The proposed multiquadratic interpolation is evaluated by comparing it with the other methods by calculating the root mean squared error and processing time means.

International audience; The watershed transform is considered as the most appropriate method for image seg-mentation in the field of mathematical morphology. In the following paper, we present an adapted topological watershed algorithm suited for a rapid and effective implementation on Shared Memory Parallel Machine (SMPM). The introduced algorithm allows a parallel watershed computing while preserving the given topology. No prior minima extraction is needed, nor the use of any sorting step or hierarchical queue. The strategy that guides the parallel watershed computing, labeled SDM-Strategy (equivalent to Split-Distributes and Merge), is also presented. Experimental analyses such as execution time, performance enhancement , cache consumption, efficiency and scalability are also presented and discussed.

International audience; This special issue on Real-Time Processing of Medical Images addresses the current state-of-the-art in the field of parallel programming for medical imaging applications and the future trends in real-time medical image processing, including parallel computing (computational models, parallel algorithms and hierarchical memory optimizations), real-time implementation of embedded medical image processing applications on dedicated architectures and/or parallel architectures. We are very grateful to the reviewers who provided valuable comments and suggestions to improve the quality of the papers accepted for this special issue. Brief outlines of these papers are stated below: The first paper by Yee Hui Lee, Mohamed Khalil-Hani, Rabia Bakhteri and Vishnu P. Nambiar presents a real-time image acquisition system with an improved image quality assessment module to acquire high quality Near Infrared Images. The NIR image quality assessment module utilizes improved two-dimensional entropy and mask-based edge detection algorithms. In this work, the effectiveness of the proposed NIR image acquisition system is demonstrated through the implementation of a complete finger-vein biometric authentication system. The proposed module is implemented as an embedded system on a Field Programmable Gate Array (FPGA). The proposed system is able to achieve a recognition accuracy of 0.87% equal error rate (EER) and can handle real-time processing at 15 frames/second. The second paper by Faten Chaieb, Tarek Ben Said, Sabra Mabrouk and Faouzi Ghorbel presents a segmentation method from four-phase computed tomography images. The proposed method is based on the combination of the Expectation – Maximization algorithm and the Hidden Markov Random Fields. The segmentation method is applied on a Volume Of Interest (VOI) that decreases the number of processed voxels. In order to accelerate the classification steps within the segmentation process, a bootstrap resampling scheme is applied. The proposed method is speeded up by adopting a bootstrap sampling approach on a semi-automatic selected VOI.

Background The sequence of Q, R, and S peaks (QRS) complex detection is a crucial procedure in electrocardiogram (ECG) processing and analysis. We propose a novel approach for QRS complex detection based on the deterministic finite automata with the addition of some constraints. This paper confirms that regular grammar is useful for extracting QRS complexes and interpreting normalized ECG signals. A QRS is assimilated to a pair of adjacent peaks which meet certain criteria of standard deviation and duration. Results The proposed method was applied on several kinds of ECG signals issued from the standard MIT-BIH arrhythmia database. A total of 48 signals were used. For an input signal, several parameters were determined, such as QRS durations, RR distances, and the peaks’ amplitudes. σRR and σQRS parameters were added to quantify the regularity of RR distances and QRS durations, respectively. The sensitivity rate of the suggested method was 99.74% and the specificity rate was 99.86%. Moreover, the sensitivity and the specificity rates variations according to the Signal-to-Noise Ratio were performed. Conclusions Regular grammar with the addition of some constraints and deterministic automata proved functional for ECG signals diagnosis. Compared to statistical methods, the use of grammar provides satisfactory and competitive results and indices that are comparable to or even better than those cited in the literature.

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [Formula: see text] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network’s size and the input data vectors’ dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A [Formula: see text] SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297[Formula: see text]MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one.

Watershed transform is widely used in image segmentation. In literature, this transform is computed by various algorithms among which the M-border kernel algorithm [1]. This algorithm computes the watershed transform in the framework of edge weighted graphs. It is based on a local property that makes it adapted to parallelization. In this paper we propose a parallel implementation of this algorithm. We start by studying the data dependencies problematic that it raises. We give then an approach that allows overcoming this problematic based on an alternated edges processing strategy. The implementation of this strategy on a shared memory multicore architecture using a Single Program Multiple Data (SPMD) approach proves its effectiveness. In fact, experimental results show that our implementation achieves a relative speedup factor of 2.8 using 4 processors over the performance of the sequential algorithm using a single processor on the same system.

International audience; Accurate coronary artery segmentation is a fundamental step in various medical imaging applications such as stenosis detection, 3D reconstruction and cardiac dynamics assessing. In this paper, a MultiScale Region Growing (MSRG) method for coronary artery segmentation in 2D X-Ray angiograms is proposed. First, a region growing rule which incorporates both vesselness and direction information in a unique way is introduced. Then an iterative multiscale search based on this criterion is performed. Selected points in each step are considered as seeds for the following step. By combining vesselness and direction information in the growing rule, this method is able to avoid blockage caused by low vesselness values in vascular regions, which in turn, yields continuous vessel tree. Performing the process in a multiscale fashion helps extracting thin and peripheral vessels often missed by other segmentation methods. Quantitative evaluation performed on real angiography images shows that the proposed segmentation method identifies about 80% of the total coronary artery tree in relatively easy images and 70% in challenging cases with a mean precision of 82% and outperforms others segmentation methods in terms of sensitivity. The MSRG segmentation method was also implemented with different enhancement filters and it has been shown that the Frangi filter gives better results. The proposed segmentation method has proven to be tailored for coronary artery segmentation. It keeps an acceptable performance when dealing with challenging situations such as noise, stenosis and poor contrast.

This paper presents a robust method of local deformation analysis of the heart's left ventricle (LV) aimed at specifying the affected area. Our method is based on regional curvature variation calculation using the Hotelling T2 two samples difference metric. It has been validated with real data obtained from myocardial scintigraphy imaging techniques of 44 patients. For each patient we extract 3D surfaces representing the anatomical structures of interest, namely the endocardium and epicardium at stress. In order to progress to a regional analysis, we carried out, for each patient, a division into 17 regions according to the AHA standard. Experimental results demonstrate the great robustness and efficiency of our method.

International audience; In this paper, a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware 5 × 5 SOM was validated through the FPGA implementation and its performances at a working frequency of 200MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.

International audience; — Multidimensional retiming is an efficient optimization approach that ensures increasing a parallelism level in order to optimize the execution time. Two existing techniques called incremental and chained multidimensional retiming are based on this approach, which aim at achieving a full parallelism on loop body in order to schedule applications with a minimum cycle period. However, the cycle number increases in terms of parallelism level which presents a limiting factor to respect the execution time constraint of real-time applications. In this paper, we show how the minimal cycle period is achieved in multidimensional applications without applying a full parallelism. We present the theory of a novel technique, called delayed multidimensional retiming. Firstly, two efficient algorithms are presented where the first one insures the extraction of timing and data dependency properties of the application and the second one selects the set of data path for retiming. Then, we propose theorems to deduce a retiming function for the selected paths. Finally, a third algorithm describing the optimization approach is introduced. The experimental results show that our technique improves execution times in comparison to existing techniques. It achieves average improvements on the execution time of 41.57% compared to the Incremental technique and 11.55% compared to the Chained technique.

International audience; Image processing technology has grown significantly over the past decade. Its application on low-power mobile devices has been the interest of a wide research group related to newly emerging contexts such as augmented reality, visual search, object recognition, and so on. With the emergence of general-purpose computing on embedded GPUs and their programming models like OpenGL ES 2.0 and OpenCL, mobile processors are gaining a more parallel computing capability. Thereby, the adaptation of these advancements for accelerating mobile image processing algorithms has become actually an important topical issue. In this paper, our interest is based on reviewing recent challenging tasks related to mobile image processing using both serial and parallel computing approaches in several emerging application contexts.

International audience; — Nested loops present the most critical sections in several embedded real-time applications. To achieve a higher performance, the design process employs an optimization technique in order to increase parallelism. However, the nested loop codes rise greatly in terms of parallelism level. Due to tight execution time constraints, each optimization technique produces implementations with an important code size. This criterion presents a limiting factor to implement the provided results in embedded real-time systems. In this paper, we propose a novel optimization approach that combines the delayed multidimensional retiming and loop striping techniques. It explores the solution space, which is composed by all parallelism cases proposed by both techniques, in order to provide the implementation that achieves the execution time constraint while uses a lower code size. In this context, we present the theory of combining both techniques. Then, we propose efficient algorithms that ensure selecting a set of parallelism transformations, based on their execution time and code size evolutions. The experimental results show that our optimization approach provides optimal solutions compared to those provided by applying only one technique. It achieves average improvements on the code size of 35.21% compared to the delayed multidimensional retiming and 16.38% compared to the loop striping.

International audience; Field Programmable Gate Arrays (FPGA) are flexible, so they are commonly used in many high speed applications. However, power constraints are the most important limiting factors while implementing high speed adaptable applications. This work addresses the optimization of the execution time and power consumption. We propose a new design methodology by extending Algorithm-Architecture-Adequacy (AAA) methodology. It provides an implementation which meets real time constraints and allows the designer to optimize power consumption or material resources. The extension has been implemented in AAA software tool called Synchronized Distributed Executive for Integrated Circuits (SynDEx-IC). The experimental results show that the mentioned software tool provides an architecture that consumes less power among the explored ones, which the average power is reduced by 15.75%.

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.

Colloque avec actes et comité de lecture. internationale.; International audience; This paper presents an area-saving parallel implementation of a Self-Organizing Map neural network (SOM) on FPGA. The purpose is to make available a finer grain of parallelism to be used in massively SIMD parallel SOM system architectures. We have handled a serial arithmetics (Most Significant Bit First: MSBF and Least Significant Bit First: LSBF), to process the different mathematical operations. Above all, our work has been oriented in such a way to get a light, easy to wear system for classification of vigilance states in humans from electroencephalographic (EEG) signals. The performances of our implementation in terms of area, speed and especially power consumption are highly satisfactory.