Search

A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to increase the ADC immunity to input signal characteristics. Enhanced offset and time-skew calibration algorithms are developed to maximize the performance in the presence of non-ideal sampling switches. At 5GS/s, the ADC dissipates 641mW while achieving a 62dB and 57dB of SFDR and SNDR respectively while maintaining a SFDR excluding HD2 and HD3 better than 70dBc across the first Nyquist band for input amplitudes down to −20dBFS.

This work presents direct-RF TX/RX modular tiles for monolithic integration in 16nm FinFET. The TX tile embeds 4 baseband-to-RF signal chains with 14-bit 9GS/s DACs while the RX tile provides 2 RF-to-baseband signal chains with 13-bit 4.5GS/s ADCs. Each tile includes a low-noise PLL [1] and can support full Nyquist bandwidth. The TX path demonstrates better than −67dBc ACPR when synthetizing a half-loaded band 42 and consumes 700mW. The RX path shows an EVM of 11.6% for the in-band blocking test of the 3.5GHz band and consumes 747mW. These tiles have been integrated in a 372mm2 FPGA SoC and demonstrate better than 90dB digital-to-analog isolation and sub-80ps channel alignment.

In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM Cortex-53 and dual ARM Cortex-R5 processing subsystem, 750K programmable logic cells, 4000 DSP slices and 4 32Gb/s serial transceivers. Each 14-bit RF-DAC operates at a sample rate of up to 6.4GS/s and can directly synthesize RF carriers up to 4GHz. Each 12-bit RF-ADC operates at a sample rate of up to 4GS/s and can directly digitize RF carriers up to 4GHz. Other RF functions generally associated with analog / RF such as complex mixing and filtering have also been integrated and implemented in the digital domain (digital-RF), enabling lower system cost and power and increased flexibility.

In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integrator-based amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability and support production testability.