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In a successive-approximation-register (SAR) ADC, comparator noise is often one of the dominant error sources. In this brief, the relation between the input referred noise of a comparator and its resulting noise in an SAR ADC is presented. A scaling factor less than unity is found when the comparator noise is referred back to the ADC input. When the comparator contains both thermal and flicker noise, the noise profile is maintained when referred back to the ADC input; however, due to aliasing caused by sampling, the flicker noise corner at the ADC output is pushed toward lower frequencies compared with the flicker noise corner frequency of the comparator. The results are analytically derived and proven by simulation and measurement.

This paper describes a high-resolution energy-efficient CMOS temperature sensor, intended for the temperature compensation of MEMS/quartz frequency references. The sensor is based on silicided poly-silicon thermistors, which are embedded in a Wien-bridge RC filter. When driven at a fixed frequency, the filter exhibits a temperature-dependent phase shift, which is digitized by an energy-efficient continuous-time phase-domain delta-sigma modulator. Implemented in a 0.18- $\mu \text{m}$ CMOS technology, the sensor draws 87 $\mu \text{A}$ from a 1.8 V supply and achieves a resolution of 410 $\mu \text{K}_{\textrm {rms}}$ in a 5-ms conversion time. This translates into a state-of-the-art resolution figure-of-merit of 0.13 pJ $\cdot$ K2. When packaged in ceramic, the sensor achieves an inaccuracy of 0.2 °C (3 $\sigma )$ from −40 °C to 85 °C after a single-point calibration and a correction for systematic nonlinearity. This can be reduced to ±0.03 °C (3 $\sigma )$ after a first-order fit. In addition, the sensor exhibits low 1/ $f$ noise and packaging shift.

A delta-sigma modulator architecture reducing the impact of the digital-to-analog converter (DAC) non-linearity in a multi-bit delta-sigma DAC is presented. By cascading and deterministic dithering, only small signals are processed by the multi-bit DAC, thus a large dynamic range can be maintained; by suppressing the out-of-band noise before being processed by the multi-bit DAC, less shaped-noise gets inter-modulated by the non-linear DAC, thus the raise of noise floor is reduced. The proposed architecture provides a practical way to implement a high-resolution multi-bit delta-sigma DAC at low over-sampling rate (OSR). System level simulations in MATLAB show that an average ENOB=14.5-bits can be achieved with 0.2% (standard deviation) DAC element mismatch at OSR = 10.