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This letter presents a CMOS reverse received signal strength indicator (reverse-RSSI) based logarithmic power detector (PD). A capacitor attenuation array and unbalanced source-coupled rectifiers are utilized to constitute the reverse-RSSI architecture, which greatly increases the maximum detectable power. Two auxiliary capacitors in the rectifier are introduced to improve linearity at high input power dramatically. The PD with 0.4–5-GHz operating frequency can be fully integrated and has stable and reliable performance according to multiple tests. Measurement results show that the maximum detectable power achieves +35 dBm and dynamic range reaches 45 dB with ±1-dB linearity error. The proposed PD is implemented in a standard 180-nm CMOS process with 0.085 mm2 core area. The total static power consumption is 0.78 mW with a 3.3-V supply voltage.

A fully CMOS integrated low TX noise UHF RFID digital transmitter with tunable directional coupler is proposed. The transmitter decreases the AM noise density to −144.6 dBc/Hz at 10 kHz offset by eliminating noisy conventional analog components and optimizing LO chain. The tunable transformer-based directional coupler which is feasible for CMOS integration exhibits high isolation performance of −55 dB over the entire band. The transmitter with quadrature DPA structure supports DSB/SSB/PR-ASK modulation, and with the directional coupler, it achieves 22.8 dBm peak power with drain efficiency of 37.8%. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1750–1756, 2016

An on-chip broadband self-interference canceller based on the electrical balance of hybrid transformers is proposed in this work. A variable inductor based on-chip balanced impedance network is utilized to match the actual antenna impedance varying with frequency. In order to achieve broadband electrical balance, an auxiliary quadrature digital transmitter is used to compensate variations of the antenna impedance with frequency. The proposed technique is demonstrated in a standard 130 nm CMOS 1P8M process and the chip occupies 4.84mm2. The simulation results show that the demonstration achieves isolation of more than 60 dB over a 25 MHz bandwidth with 23 dBm transmitter output power at 2 GHz.

A novel self-turnoff control circuit for program process of one-time programmable (OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown of OTP cell. The simulation results show that the average power consumption of proposed circuit decreases to about 3nA in the whole program process.

This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages including normal charge, discharge, pre-charge and hold stage, the threshold voltage of comparators is adjusted dynamically. A 32.7-kHz relaxation oscillator with the proposed half-period pre-charge compensation scheme is implemented in a TSMC 0.18-μm CMOS process, occupying a silicon area of 0.048 mm2. Simulation results show that the proposed relaxation oscillator consumes 51-nW at room temperature from 0.6-V power supply, and temperature stability of 43.1 ppm/°C from −55 °C to 125 °C and ±0.60% frequency variation with supply voltage from 0.5 V to 1.0 V are achieved.

This paper proposes a DC-DC buck converter with all-pass network based passive level shifter in 55nm standard CMOS process, for battery powered portable applications. In order to handle high battery voltages in this advanced standard CMOS process, a passive level shifter based on all-pass network is applied for gate oxide protection. Drain extension is proposed to obtain high breakdown voltage of active region. The proposed buck converter with the passive level shifter works in DCM operation as its load current varies from 0.1–10mA. The buck converter achieves a peak efficiency of 93.7% and 83.8% at 10mA load current, with a supply voltage of 1.8V and 3.7V, respectively.

In nature and society, there exist many learning modes; thus, in this paper the goal is to incorporate features from the social organizations to improve the learning of intelligent systems. Inspired by future prediction, in the high level, the discrete dynamics is further written into the equivalent prediction model which can provide the bridge from now to the future. In the low level, the efficiency could be improved in way of group learning. The philosophy is integrated into discrete neural flight control where the cascade dynamics is written into the prediction form and the minimal-learning-parameter technique is designed for parameter learning. The effectiveness of the proposed method is verified with simulation.