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This article presents an attack-resilient architecture for cyber-physical systems (CPSs). As a case study, the authors build a radio-based train control testbed and validate the proposed resilient design architecture. The target CPS application is a hierarchical control system.

This paper presents an architecture for cyber-physical systems resilient against external attacks and internal faults. The target CPS consists of multiple physical systems equipped with local embedded systems, a supervision module that oversees operations of the physical systems, and communication network connecting each physical system to the supervision module. We give an instantiation of the architecture on a radio-based train control system to demonstrate the resiliency under various safety critical scenarios. The testbed entitled KRS-DGIST includes a commercial train control and supervision software deployed in the Philippines. The railway installed sensors and other mechanisms are implemented reflecting the actual train control and supervision system, and the dynamics of the trains is computer simulated. Demonstrations are given with attacks on sensors, communication network, and embedded systems.

We propose a dynamic vehicular routing algorithm with traffic prediction for improved routing performance. The primary idea of our algorithm is to use real-time as well as predictive traffic information provided by a central routing controller. In order to evaluate the performance, we develop a microtraffic simulator that provides road networks created from real maps, routing algorithms, and vehicles that travel from origins to destinations depending on traffic conditions. The performance is evaluated by newly defined metric that reveals travel time distributions more accurately than a commonly used metric of mean travel time. Our simulation results show that our dynamic routing algorithm with prediction outperforms both Static and Dynamic without prediction routing algorithms under various traffic conditions and road configurations. We also include traffic scenarios where not all vehicles comply with our dynamic routing with prediction strategy, and the results suggest that more than half the benefit of the new routing algorithm is realized even when only 30% of the vehicles comply.

Storage I/O performance remains a key factor that determines the overall user experience of a computer system. This is especially true for mobile systems as users commonly browse and navigate through many high-quality pictures and video clips stored in their device. The appetite for more appealing user interface has continuously pushed the mobile storage interface speed up; emerging UFS 2.0 standard provisions a maximum bandwidth of as high as 1,200 MB/s. In this work, we propose, design, and implement a mobile storage architecture that leverages the high-speed DRAM interface for communication, thus substantially expanding the storage performance headroom. In order to effectively turn the existing DRAM interface into a storage interface, we design a new storage protocol that runs on top of the DRAM interface. Our protocol builds on a small host interface buffer structure mapped to the system's memory space. Based on this protocol, we develop and fabricate a storage controller chip that natively supports the LPDDR3 interface. We also develop a host software stack (Linux device driver and boot loader) and a host platform board. Finally we show the feasibility of our proposal by constructing a full Android system running on the developed storage device and platform. Our detailed evaluation shows that the proposed storage architecture has very low protocol handling overheads and compares favorably to a UFS 2.0 device. The proposed architecture obviates the need for implementing a separate host-side storage controller on a mobile CPU chip.