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This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of $2.9\mu \text{s}$ and $4.2\mu \text{s}$ for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation.

This paper presents a learning algorithm for a vector-matrix multiplier (VMM) + k-winner-take-all (WTA) classifier one-layer architecture on a large-scale field programmable analog array (FPAA). The technique enables opportunities for embedded, ultra-low power machine learning, techniques typically considered for large servers. To develop this training algorithm, this paper starts by understanding fundamental equivalent transformations for the VMM + WTA classifier networks. A VMM+ WTA structure can exactly compute a self-organizing map (SOM) or vector quantization (VQ) operation, in addition to other transformations. SOM, VQ, and Gaussian mixture models learning concepts are utilized for the training algorithm of this single one-layer network. An on-chip clustering step determines the initial weight set for ideal target and background values. Null symbols are important for the algorithm and are set from midpoints of the target values. The results are shown both as numerical simulation of the VMM+WTA learning network, illustrating some numerical differential equation simulation limitations for this problem, as well as experimental measurements implemented on an system on chip FPAA device.

This paper focuses on the circuit aspects required for an on-chip, on-line system on chip large-scale field-programmable analog array learning for vector-matrix multiplier (VMM) + winner-take-all (WTA) classifier structure. We start by describing the VMM+WTA classifier structure, and then show techniques required to handle device mismatch. The approach is initially explained using a VMM+WTA as a two-input XOR classifier structure. The approach requires considering the entire mixed-mode system, including the analog classifier data path, control circuitry for weight updates, and digital algorithm for computing digital weight updates and resulting floating-gate programming during the algorithm.

This brief investigates temperature compensation techniques for circuits and systems on a reconfigurable platform. The work demonstrates use of large-scale reconfigurable system-on-chip for reducing the variability of circuits and systems compiled on a floating gate (FG)-based field-programmable analog array (FPAA). The work presents current and voltage reference which could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment, which could be easily compiled on the FPAA. An FG-based current reference is then used for biasing a second-order $G_{m}-C$ bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large-scale FG FPAA presented here is fabricated in 350-nm CMOS process.

We present a calibration flow for a large-scale floating-gate (FG) system-on-chip field programmable analog array. We focus on characterizing the FG programming infrastructure and hot-electron injection parameters, MOSFET parameters using the EKV model, and calibrating digital-analog converters and analog-digital converters. In addition, threshold voltage mismatches on FG devices due to their indirect structure are characterized using on-chip measurement techniques. The calibration results in enabling a digital approach, where a design can be programmed without having to deal with the local and global mismatches, on a reconfigurable analog system. This paper shows the results of a compiled nonlinear classifier block comprising a vector-matrix-multiplier and a winner-takes-all on three different calibrated chips.

This paper presents a low-power built-in self-test system to compensate for mismatch and variations in CMOS IC. The system is designed and compiled on a low-power field programmable analog array (FPAA) fabricated on a 350-nm CMOS process. A second-order bandpass filter is used as a device under test. A set of 12 parallel filter banks are compiled on three different FPAA chips and compensated for local mismatch and variations in the bias current, and mismatch in parasitic and routing capacitances. The bandpass filters are biased in subthreshold regime and the system of 12 parallel filter banks consumes a power of $7.072~\mu \text{W}$ . The proposed tuning algorithm reduces variation in center frequency to 5.07% compared with a variation of 10.16% when they are not tuned, variation in quality factor to 8.52% from 13.86%, and variation in the gain at the center frequency to 3.83% from 21.04%. These values are deviation of the parameters from its mean for the data taken from three different FPAA chips fabricated on the same wafer.

This work presents a mixed-signal physical-compu-tation-electronics for monitoring three vital signs; namely heart rate, blood pressure, and blood oxygen saturation; from electrocardiography, arterial blood pressure, and photoplethysmography signals in real-time. The computational circuits are implemented on a reconfigurable and programmable signal-processing platform, namely field-programmable analog array (FPAA). The design leverages the core enabling technology of FPAA, namely floating-gate CMOS devices, and an on-chip low-power microcontroller to achieve energy-efficiency while not compromising accuracy. The custom physical-computation-electronics operating in CMOS subthreshold region, performs low-level (i.e., physiologically-relevant feature extraction) and high-level (i.e., detecting arrhythmia) signal processing in an energy-efficient manner. The on-chip microcontroller is used (1) in the programming mode for controlling the charge storage at the analog-memory elements to introduce patient-dependency into the system and (2) in the run mode to quantify the vital signs. The system has been validated against digital computation results from MATLAB using datasets collected from three healthy subjects and datasets from the MIT/BIH open source database. Based on all recordings in the MIT/BIH database, ECG R-peak detection sensitivity is 94.2%. The processor detects arrhythmia in three MIT/BIH recordings with an average sensitivity of 96.2%. The cardiac processor achieves an average percentage mean error bounded by 3.75%, 6.27%, and 7.3% for R-R duration, systolic blood pressure, and oxygen saturation level calculations; respectively. The power consumption of the ECG, blood-pressure and photo-plethysmography processing circuitry are 126 nW, 251 nW and 1.44 μW respectively in a 350 nm process. Overall, the cardiac processor consumes 1.82 μW.

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor ( $\mu \text{P}$ ) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 $\mu \text{W}$ to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 $000\times $ higher density than other non-FG approaches.

This paper presents a low-power speech detector on a fully reconfigurable Field Programmable Analog Array (FPAA). The entire system is designed and compiled on a FPAA fabricated in 0.35μm CMOS process. The system uses 12 parallel bank of band-pass filters to extract features. The outputs of the filter bank are used by a single layer of 12×2 Vector Matrix Multiplication (VMM) and Winner Take All (WTA). The weights are stored on the VMM using pFET floating gate transistor. The power consumption of the analog system is 155.6μW with a 2.5 V power supply. The low power consumption allows the use of such a system for portable and remote sensing applications. Further, the paper investigates the performance of the system by adding white gaussian noise to the input signal. The system has an accuracy of 99.94% when the input has a SNR of 20dB and of 74% with a SNR of 8dB.

We present our junior level class implementation moving from classical discrete circuit concept towards system level design. This approach was enabled using large-scale Field Programmable Analog Arrays (FPAA) (ECE 3400). The approach enables a first junior level transistor circuit course to build and verify system level designs. This course heavily utilized remote FPAA designs for their hands-on projects; the resulting class data usage generated by this system gives some information on class behavior. This discussion presents the implementation, analysis, and early assessment data for this first semester class.

We present a System-On-Chip Field Programmable Analog Array (FPAA) for analyzing and processing the signals off an accelerometer for a wearable joint health assessment device. FPAAs have been shown to compute with an efficiency of 1000 times, as well as area efficiencies of 100 times, more than digital solutions. This work presents a low power signal processing system which allows us to extract features from the output of the accelerometer. These features are used by the classifier, implemented using a vector matrix multiplication and a two output 1-winner-take-all, to detect flexion and extension cycles in the subject. The compiled design consumes 0.636 μW of power for the front end analog signal processing chain where as the single layer classifier uses 13 μW of power. Thus the system is highly suitable for wearable applications where power consumption is a major concern. The current FPAA is fabricated in a 0.35 μm CMOS process and is operated at a power supply of 2.5 volts. The Gm-C filters and other circuits are operated in the subthreshold regime of the transistor to obtain the highest transconductance to current ratio offered by the process.

A proof-of-concept low-power analog classifier for assessing acoustic signals from the knee joint on a reconfigurable Field Programmable Analog Array (FPAA) is presented in this paper. Knee joint sounds are measured using piezoelectric (contact) microphones and processed using the front end analog filters. A single layer of neural network composed of Vector Matrix Multiplication (VMM) and Winner-Take All (WTA) is used for the classification. A simple classifier detecting an anterior cruciate ligament injury is implemented here. Measurement from a single subject's healthy and injured knees are used here as an input. The FPAA is fabricated in a 350nm CMOS process. A bank of 12 parallel filters is used for feature extraction and a 12×2 VMM-WTA is used as a classifier. The compiled system, front-end and the classifier, consumes a power of 15.29μW with a power supply of 2.5 V.

This demonstration presents live hands-on experience of the System on Chip (SoC) large-scale Field Programmable Analog Array (FPAA) IC [1] through a complete PC Board and high-level tool interface [2]. Figure 1a shows the demonstration requires only basic power connection to the laptop The hardware includes an FPAA demonstration board and a Digilent USB device to enable a scope / function generator functionality.

We present a novel remote test system, enabled by configurable analog-digital ICs to create a simple interface for a wide range of experiments, whether in research or educational directions. Our remote test system utilizes a nearly identical setup to the existing large-scale Field Programmable Analog Array (FPAA) toolset; a mixed-mode configurable system with a common digital interface (e.g. USB) enables a nearly seamless transition. The system overhead requirements are straightforward, requiring simple email handling, available over almost all network systems with no additional requirements. We present using the FPAA devices and baseline tool framework, present overview examples for the remote system.

We present a SoC large-scale Field Programmable Analog Array (FPAA) test system, enabled by configurable analog-digital ICs to create a simple interface for a wide range of experiments in classroom environments. This configurable system appears as a simple digital peripheral using a standard USB interface for communication and power. Combined with a high-level tool flow for on-chip application design, this FPAA device demonstrates a number of mixed-signal computations, classification, and signal processing and its impact on hands-on circuit instruction.

We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for embedded IoT devices. These techniques offer computational capability to address network security concerns. This paper begins the discussion of security opportunities for, and issues using, FPAA devices for small embedded IoT platforms. These FPAAs enable devices often utilized for low-power context aware computation. Embedded FPAA devices have both positive Security attributes, as well as potential vulnerabilities. FPAA devices can be part of the resulting secure computation, such as implementing unique functions. FPAA devices can be used investigate security of analog/mixed signal capabilities. The paper concludes with summarizing key improvements for secure ultra-low power embedded FPAA devices.

We present a novel remote test system, an integrated remote testing system requiring minimal technology support overhead, enabled by configurable analog–digital Integrated Circuits (IC) to create a simple interface for a wide range of experiments. Our remote test system requires no additional setup, resulting both from using highly configurable devices, as well as from the advancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system. The system overhead requirements require simple email handling, available over almost all network systems with no additional requirements. The system is empowered through large-scale Field Programmable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present a range of experimentally measured examples illustrating the range of user interfacing available for the remote user.