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A 3-D heterogeneous integration (3-D-HI) is poised to enable a new era of high-performance integrated circuits via a multitude of benefits, including a reduction in I/O power consumption and ability to tightly couple disparate technologies. However, a significant hurdle toward enabling a chiplet ecosystem is the standardization of 3-D die-to-die (D2D) interconnects that facilitate rapid integration. Technology-driven constraints highlighted in published works demonstrate that a unique approach to 3-D D2D interconnect design and implementation is required, while preserving the ability to customize the interconnect to accommodate future technology concerns and applications with minimal overhead. This article presents a framework to generate customized 3-D D2D interconnect physical layers (PHYs) that are simultaneously standard-compliant, physical-aware, and can be automatically integrated into all stacked chiplets. The generator framework leverages the Chisel hardware description language to allow designers to do the following: 1) compile a port list directly into a PHY; 2) automate design and physical design (PD); and 3) perform design space exploration of interconnect features (e.g., bump map pitch, clocking architecture, and others). The 3-D PHY generator framework and features detailed in this work can be used to produce a reference implementation for a standard like UCIe-3-D, representing a significant paradigm shift from current specification and design methodologies for 2.5-D D2D interconnect (e.g., UCIe) implementations. This work concludes with the results of a redundancy design space exploration tradeoff study, showing the benefits of a proposed spatial coding redundancy scheme in an example PHY using emulated 9- $\mu $ m hybrid bonding for a 4 Tx/4 Rx module array with 4:1 coding redundancy ratio.

Considering the manufacturing and packaging process, 3-D integrated circuits design often requires irregular chip structures. The 3-D integrated circuits with irregular structures can facilitate differentiated chip design and reduce manufacturing costs. Highly complex through-silicon vias have not been considered in past thermal modelling and analysis of irregularly structured 3-D integrated circuits. Thus, a detailed model of a three-layer irregularly structured 3-D integrated circuit with through-silicon vias and microbumps is developed, and an analytical method based on the thermal resistance network model is proposed to extract the equivalent thermal conductivity of through-silicon vias and microbumps, the accuracy of which is verified by a 3-D finite element simulation method. The results show that the maximum temperature and temperature gradient obtained by the equivalent model simulations agree well with the detailed model results, proving the validity of the equivalent model. To save the computational cost, the effects of heat source area, power setting and through-silicon vias structure parameters on the maximum temperature are studied by numerical simulation method based on the equivalent model. Heat source area equal to the overlap between chip layers, high power chips close to the heat sink, and reducing through-silicon vias pitch can better reduce the maximum temperature. The results provide a reference value for thermal design and optimization of 3-D integrated circuits with irregular structures. [ABSTRACT FROM AUTHOR]

In a 2-D design, the block pins are located at the periphery of a block optimally since blocks are placed side-by-side horizontally in a single placement layer. However, monolithic 3-D (M3D) integration relieves this boundary constraint by allowing vertical block communication between different tiers based on an nm-scale pitch of 3-D interconnection. In this article, we present a design methodology named pin-in-the-area that assigns block pins at any position inside the boundary of a block using commercial 2-D place-and-route (P&R) tools and enables an efficient block implementation and integration for a block-level M3D integrated chips (ICs). Our pin-in-the-area starts from the netlist restructuring and connectivity-aware tier-by-tier chip planning, which defines blocks and decides their sizes and $(X,Y,Z)$ locations for a two-tier M3D design. Next, we perform wirelength-driven 3-D placement to minimize 3-D half-perimeter wirelength (HPWL) and find optimal pin locations inside the boundary of a block. Once block designs are done, we apply the unique macro handling scheme to the top-level timing closure. Based on a 28-nm two-tier M3D hierarchical design result, we show that our solution offers 13.6% and 24.7% energy-delay-product reduction compared to the M3D design with pins assigned at the block boundaries and its 2-D counterpart, respectively.

The dc and high-frequency performance of p-type polycrystalline silicon (poly-Si) finlike thin-film transistors (FinTFTs) with various wide drain region designs are investigated herein. The poly-Si FinTFT with the triangular wide drain design exhibits a high ION/IOFF current ratio (<107) and high cutoff frequency (ƒT= 371.5 MHz at VDS = −1 V). This structure has lower drain series resistance Rd than does the conventional poly-Si FinTFT and lower gate-to-drain capacitance Cgd than does the poly-Si FinTFT with the hybrid wide drain design. This result indicates the possible use of poly-Si TFT technology for radio frequency integrated circuits and the great potential for future use in 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

This paper applies the multi-layer graphene nanoribbon as a new prospective filler material for through silicon via to solve the complex heat problems in the 3-D integrated circuits. An equivalent thermal model for 3-D integrated circuits with the MLGNR-based through silicon via is presented in this work, which take lateral heat transfer of through silicon via into account. The experimental results show that the heat transfer performance of MLGNR-based through silicon via is better than the conventional Cu-based through silicon via. Furthermore, it is found that the temperature predicted by the proposed model are in good accordance with the ANSYS simulation, and the maximum relative deviation is less than 4.0%. [ABSTRACT FROM AUTHOR]

In this paper, we have developed multilayer bonding technology to stack complementary metal–oxide semiconductor (CMOS) circuits. The steps include repeated embedding of gold (Au) electrodes, hybrid bonding of Au and SiO2 on a silicon-on-insulator (SOI) substrate using surface activation with O2 plasma, and subsequent elimination of the Si substrate. Furthermore, the characteristics of Au/SiO2 hybrid bonding via O2 plasma are tested with the fabrication of a triple-stacked daisy-chain test device using 3- $\mu \text{m}$ -diameter Au electrodes at a pitch of $6~\mu \text{m}$. When the surface is activated using O2 plasma before bonding, the bonding strength increases approximately four times stronger than that when the surface activation is performed with sequential plasmas of Ar and O2. This additional strength ensures that the bonded interface remains intact while the layers are stacked. A prototype device is manufactured with alignment errors of approximately $0.4~\mu \text{m}$ at the center and approximately 1 $\mu \text{m}$ at the corners. No voids are seen in the two bonded interfaces, and more than 984 000 Au contacts are produced, each having an average resistance of 92.8 $\text{m}\Omega $. These results indicate that the proposed multilayer stacking technology is promising for developing high-performance 3-D integrated circuits, 3-D integrated CMOS image sensors, and microelectromechanical systems based on SOI substrates. [ABSTRACT FROM AUTHOR]

We have developed a quarter video graphics array (QVGA) digital pixel image sensor by using the 3-D integration technology. The pulse-frequency modulation (PFM) analog-to-digital converter (ADC) operates as a digital pixel, which overcomes the signal saturation due to the full well capacity of the photodiode (PD). We have also newly designed a PFM-ADC for pixels with a pinned PD and a floating diffusion to comply with the CMOS image sensor process used to attain high sensitivity and low noise. PDs, comparators, logic circuits, and counters are integrated into two silicon-on-insulator layers by pixel-wise 3-D integration with gold electrodes with a ${5}~\mu \text{m}$ diameter, thereby achieving a QVGA resolution for a 20-mm square chip in the 0.18- and 0.2- $\mu \text{m}$ process nodes. The developed sensor exhibits both the excellent linearity and a wide-dynamic range of more than 96 dB. Video images with a high bit depth of 16 bit are also obtained to demonstrate the superior image sensing, capable of capturing the real world at high fidelity. [ABSTRACT FROM AUTHOR]

Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs can be utilized for test application. As a result, TSVs become the bottleneck for transferring the large volume of test-data to the various layers of the stack, and the time for testing the 3-D chip increases a lot. In this paper, we propose an efficient test-access mechanism (TAM) architecture that exploits the high speed of TSVs to minimize the time for testing 3-D SoCs. The proposed TAM architecture is based on a 2-D time-division-multiplexing approach, and by the means of a very effective test-scheduling method, it offers significant savings in test-time, TSV-count and TAM-cost under power and thermal constraints. Extensive experiments on two 3-D benchmark SoCs show the benefits of the proposed method. [ABSTRACT FROM AUTHOR]

The 3-D vertical array architecture is considered to be a promising technology for emerging nonvolatile memories. But in 3-D vertical emerging nonvolatile memories, planar parasitic elements, vertical parasitic elements, and the sneak currents of the half-selected memory cells result in the delay of the read operation and read errors. This paper refers to the case of the 3-D vertical resistive switching random access memory (RRAM) technology. A read scheme, the memory core design, and the read path are proposed or analyzed. The factors that affect the read operation are concluded. A changing-reference parasitic-matching sensing circuit is, therefore, proposed. In the proposed circuit, the reference side and the read side share similar sneak currents and read paths. Simulated in a 40-nm CMOS process, the sensing time of 128-Mb 3-D vertical RRAM is 8.54 ns compared to the conventional 34.26 ns. Monte Carlo simulations show a 130.21-ns worst sensing time compared to the conventional 401.95 ns. The read errors are reduced by 100% and 95.31% under the regular and the worst RRAM resistance, respectively. [ABSTRACT FROM AUTHOR]

Low power is considered as the driving force for 3-D ICs, yet there have been few thorough design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided design techniques and design methodologies to reduce power consumption in 3-D IC designs using a commercial grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3-D ICs, four design techniques are explored: 1) 3-D floorplanning; 2) metal layer usage control for intrablock-level routing; 3) dual-Vth design; and 4) functional unit block (FUB) folding. The benefits and challenges of multiple FUB folding are also discussed. Finally, the through-silicon via technology scaling impact on FUB folding and 3-D power benefit is examined. With the aforementioned methods combined, our 2-tier 3-D designs provide up to 52.3% reduced footprint, 27.9% shorter wirelength, 35.4% decreased buffer cell count, and 27.8% power reduction over the 2-D counterpart under the same performance. [ABSTRACT FROM AUTHOR]

Vertical stacking of thin-film transistors is an effective way to reduce the footprint of a device, thus increases transistor density in complex flexible electronic applications without reducing the feature size and resolution of the patterning tools. In this paper, we report a 3-D complementary organic FET fabricated on a plastic substrate by stacking a bottom-gate top-contact p-type transistor on a top-gate bottom-contact n-type transistor with a gate shared between the two. We used high-performance polymer semiconductors, poly [(E)-2, 7-bis (2 decyltetradecyl) 4 methyl 9 (5 (2 (5 methylthiophen 2 yl) vinyl) thiophen 2 yl) benzo [lmn] [3, 8] phenanthroline-1, 3, 6, 8 (2H, 7H)-tetraone] for n-type devices and poly [2, 5-bis (7-decylnonadecyl) pyrrolo [3, 4-c] pyrrole-1, 4 (2H, 5H)-dione-(E) 1,2 bis (5 (thiophen 2 yl) selenophen 2 yl) ethene] for p-type devices to fabricate the vertically stacked organic transistors along with a Cytop and cross-linked poly (4-vinylphenol) bilayer and Poly (Methyl Methacrylate) gate dielectric. A 3-D flexible complementary organic inverter exhibits a maximum static voltage gain of \thickapprox 18 V/V and high noise immunity of up to 60% of {V} _{\mathrm {DD}} /2. The 3-D transistors show hysteresis-free I$ – $V$ characteristics despite of low-temperature processes. Moreover, we discuss the influence of cross-linker concentration and the processing temperature of the PVP dielectric film on the degree of hysteresis in $I$ – $V$ characteristics. [ABSTRACT FROM PUBLISHER]

This paper investigates the challenges of dark silicon that impede the performance and reliability of 3-D stacked multiprocessors. It presents a multipronged approach toward addressing the thermal issues arising from high-density integration in die stacks, spanning architectural techniques, design methodologies, and runtime temperature management. Importantly, this paper provides novel insights into the causes of hotspot formation in 3-D ICs and details a practical approach toward exploring and mitigating performance-limiting thermal behavior early in the system design flow. [ABSTRACT FROM PUBLISHER]

We report a monolithically integrated 3-D metal-oxide memristor crossbar circuit suitable for analog, and in particular, neuromorphic computing applications. The demonstrated crossbar is based on Pt/Al2O3/TiO2–x/TiN/Pt memristors and consists of a stack of two passive $10\times10$ crossbars with shared middle electrodes. The fabrication process has a low, less than 175 °C, temperature budget and includes a planarization step performed before the deposition of the second crossbar layer. These features greatly improve yield and uniformity of the crosspoint devices and allows for utilizing such a fabrication process for integration with CMOS circuits as well as for stacking of multiple crossbar layers. Furthermore, the integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices’ conductance values within the dynamic range of operation. We believe that the demonstrated work is an important milestone toward the implementation of analog artificial neural networks, specifically, those based on 3-D CMOL circuits. [ABSTRACT FROM PUBLISHER]

Integrating more functionality in a smaller form factor with higher performance and lower-power consumption is pushing semiconductor technology scaling to its limits. 3-D chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronic products. Additionally, the complexity of digital designs imposes that computer-aided design algorithms are getting harder and slower. This paper introduces a framework for application implementation onto 3-D reconfigurable architectures. In contrast to existing approaches, the proposed solution is customizable according to constraints posed by the application and the target 3-D device in order to improve performance metrics. Experimental results highlight the effectiveness of our framework, as we achieve average enhancements in terms of maximum operation frequency and power consumption by 35% and 47%, respectively, as compared to state-of-the-art algorithms. [ABSTRACT FROM PUBLISHER]

We have developed for the first time a 3-D integrated CMOS image sensor with pixel-parallel analog-to-digital converters (ADCs). Photodiode (PD) and inverter layers are prepared on separate silicon-on-insulator layers and directly bonded with damascened Au electrodes. The handle layer is then removed by grinding and XeF2 vapor phase etching to expose the PD surface. The developed process is suitable for pixelwise interconnection because it allows the damascened Au electrodes to be 1 \mu \textm in diameter or less. An ADC circuit is designed based on pulse frequency modulation where pulses are generated proportional to the illumination intensity, and contains a PD, inverters, a reset transistor, and counters. A prototype 3-D integrated CMOS image sensor is also developed with 64 pixels, which acquires video images without pixel defects. A wide dynamic range of >80 dB is confirmed for the incident light intensity. The experimental results demonstrate the feasibility of pixel-level 3-D integration for high-performance CMOS image sensors. [ABSTRACT FROM AUTHOR]

The linear scaling down of NAND flash memory is approaching its physical, electrical, and reliability limitations. To maintain the current trend of increasing bit density and reducing bit per cost, 3-D flash memory is emerging as a viable solution to fulfill the ever-increasing demands of storage capacity. In 3-D NAND flash memory, multiple layers are stacked to provide ultrahigh density storage devices. However, the physical architecture of 3-D flash memory leads to a higher probability of disturbance to adjacent physical pages and greatly increases bit error rates. This paper presents a novel physical-location-aware address mapping strategy for 3-D NAND flash memory. It permutes the physical mapping of pages and maximizes the distance between the consecutively logical pages, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability. The proposed mapping strategy is applied to a representative flash storage system. Experimental results show that the proposed scheme can reduce uncorrectable page errors by 70.16% with less than 10.01% space overhead in comparison with the baseline scheme. [ABSTRACT FROM AUTHOR]

Modern 3-D multiprocessor systems-on-chip (MP-SoC) incorporate processing elements (PEs) and memories within die-stacks interconnected using through-silicon vias (TSVs). The resulting power density of these systems necessitates the inclusion of thermal effects in the architecture space exploration stage of the design process. The number and placement of TSVs influences the thermal conductivity in the vertical direction in die-stacks, and consequently these must be considered during thermal analysis. However, the special requirement of keep out zones (KOZs) for TSVs due to mechanical stress considerations complicates the design of the vertical interconnect, potentially impacting its electrical performance as well. This paper presents an integrated methodology that allows for TSV topology exploration to evaluate the best vertical interconnect structure while considering crosstalk, area overheads, and KOZ requirements using an initial system floorplan. After incorporating feedback from the exploration, the resulting vertical interconnect is included within a temperature-power simulation that estimates the thermal profile of the 3-D stack. Within this methodology, a novel power management scheme for 3-D MP-SoCs that considers both temperature as well as positional information and thermal relationships between PEs, while performing dynamic voltage-frequency scaling (DVFS), is introduced. The scheme effectively maintains smooth temperature profiles, decreases fluctuations in voltage-frequency levels, and increases the aggregate frequency of operation at a lower total power dissipation. Further, the scheme is applied to a stack partitioned into voltage islands, where it is shown to match the conventional per-core DVFS schemes in its performance. [ABSTRACT FROM AUTHOR]

Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling or the reduction of grounding impedance of silicon substrates as a whole, respectively. A two-tier 3-D IC demonstrator in a 130-nm CMOS technology was successfully tested and analyzed with respect to intra and intertier substrate noise coupling. Each tier in the stack includes digital noise source circuits (NSs) and substrate noise monitors, and embodies in-place measurements of substrate noise coupling. An equivalent circuit unifies power and substrate networks of the tiers and simulates the frequency-domain response of substrate noise coupling. Measurements and calculation with the equivalent circuit are consistent for frequency dependency of substrate noise coupling in a 3-D IC demonstrator. Intratier propagation is dominant, while intertier coupling is insignificant for low-frequency substrate noise components. Intertier coupling becomes comparable with and finally overwhelms intratier coupling as the frequency of substrate noise components increases. Substrate noise coupling in a multitier chip stack is strongly impacted by the parasitic capacitance of TSVs, while that coupling becomes predictable with the equivalent circuit of the entire stack. [ABSTRACT FROM PUBLISHER]

Three-dimensional die-stacking architectures have been proposed as a promising solution to the increasing interconnect delay that is observed in scaled technologies. Although prior research has extensively evaluated the performance advantage of moving from a 2-D to a 3-D design style, the impact of process parameter variations on 3-D designs has not been studied in detail. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully synchronous (FS) and multiple clock-domain (MCD) 3-D systems. To mitigate the impact of process variations on 3-D designs, we propose the variability-aware 3-D integration strategy for MCD 3-D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization strategy is shown to significantly outperform the FS and MCD 3-D implementations that are conventionally assembled, for example, the MCD designs assembled with the proposed integration strategy provide, on average, 44% and 16.33% higher absolute yield than the FS and conventional MCD designs, respectively, at the 50% yield point of the conventional MCD designs. [ABSTRACT FROM PUBLISHER]

Through-silicon vias (TSVs) contribute to substrate noise in 3-D ICs, causing performance degradation of neighboring active devices and requiring keep-out zones. To mitigate TSV-induced substrate noise, we propose a new device, the ground (GND) plug, a TSV-like structure that connects to the ground and extends partially or completely through the substrate. We propose two types of GND plugs: a “front-side” plug, connecting to local interconnect of the same die, and a “back-side” plug, connecting to the GND from the substrate side of the die. We perform comprehensive analyses to evaluate the performance of GND plugs for two substrate types, a high-R bulk and a bulk with epitaxial layer. We compare the GND plug technique with existing noise mitigation techniques: a thicker dielectric liner, a guard ring, and a back-side ground plane. When compared with increased dielectric thickness, the front-side GND plug offers a relative 33% area reduction and allows a significantly reduced keep-out zone. The GND plug offers a more practical noise isolation approach than using a back-side ground plane. Our study demonstrates that the GND plug is a superior technology, effective in mitigating TSV-induced substrate noise by an order of magnitude when compared to the other techniques. The back-side GND plug does not compete with active devices for silicon area yet reduces substrate noise significantly. [ABSTRACT FROM PUBLISHER]

In this paper, we present a high-quality analytical 3-D placement framework. We propose using a Huber-based local smoothing technique to work with a Helmholtz-based global smoothing technique to handle the nonoverlapping constraints. The experimental results show that this analytical approach is effective for achieving tradeoffs between the wirelength and the through-silicon-via (TSV) number. Compared to the state-of-the-art 3-D placer ntuplace3d, our placer achieves more than 20% wirelength reduction, on average, with a similar number of TSVs. Furthermore, we extend this analytical 3-D placement framework with thermal awareness. While 2-D thermal-aware placement simply follows uniform power distribution to minimize temperature, we show that the same criterion does not work for 3-D ICs. Instead, we are able to prove that when the TSV area in each bin is proportional to the lumped power consumption of that bin and the bins in all tiers directly above it, the peak temperature is minimized. Based on this criterion, we implement thermal awareness in our analytical 3-D placement framework. Compared with a TSV oblivious method, which only results in an 8% peak temperature reduction, our method reduces the peak temperature by 34%, on average, with slightly less wirelength overhead. These results suggest that considering the thermal effects of TSVs is necessary and effective during the placement stage. [ABSTRACT FROM AUTHOR]

Fully depleted silicon-on-insulator (FDSOI) technology boosts the opportunity to make 3-D ICs with ultrahigh integration density, due to the short and tiny through-oxide vias (TOVs), which are made after removing the entire silicon under the buried-oxide layer. This work, for the first time, develops compact physical models for the capacitance of the TOV and the coupling capacitance between the TOV and active regions in the presence of periodical power/ground lines, from fundamental electrostatic considerations. Calculation results from the models show good agreement with the simulation results from a full-3-D capacitance solver. The models are further used to analyze the threshold voltage (Vth) variation in the FDSOI MOSFETs. The TOV in FDSOI and the through-silicon via (TSV) in bulk-CMOS-based 3-D ICs are finally compared in terms of the self-impedance as well as their impact on MOSFET Vth variation through capacitive noise coupling. These results provide important insights to TOV/TSV design and optimization in emerging 3-D ICs. [ABSTRACT FROM AUTHOR]

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (\mu-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <50∼\mum at the outermost region of the packaging structure without \mu-bumps significantly reduces approximately 2 \mum of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF. [ABSTRACT FROM AUTHOR]

The elastic anisotropy of copper through-silicon vias (TSVs) and its impact on performance and reliability in 3-D integrated structures is examined. Copper TSVs exhibit significant amount of elastic anisotropy, particularly for TSVs with very small diameters. The elastic anisotropy manifests itself in terms of different Young's moduli in different directions and results in orientation-dependent stress distributions. The copper anisotropy in TSVs is measured, and the impact on stress-induced mobility variation and structural reliability is examined using an advanced technology computer-aided design simulator. It is observed that both the charge carrier mobility and the structural reliability are affected by the anisotropy and its orientation. The copper anisotropy effects studied here become more prominent for TSVs with small diameters and/or large aspect ratios, and need to be assessed thoroughly in order to design robust 3-D structures. [ABSTRACT FROM PUBLISHER]

A methodology for DC–DC conversion in three-dimensional (3-D) circuits is described in this paper. The proposed approach exploits both linear and switching buck converters with different conversion ranges, thereby increasing power efficiency. By replacing the traditional LC filter within a switching converter with a distributed filter, a significant increase in efficiency is demonstrated. Additionally, the physical structure of the filter simultaneously enables the distribution of high current to the load while filtering the switching signal at the input. Design guidelines and expressions are developed, achieving good agreement with simulations based on the MIT Lincoln Laboratories CMOS/SOI 180-nm 3-D technology. The proposed converter distributes 2.5 A maximum current, achieving conversion from 3.3 V to 2.5 V and 1 V with, respectively, 74% and 44% power efficiency. [ABSTRACT FROM PUBLISHER]

This paper introduces a fully analytical and physical model capable of extracting high-frequency series impedance of through-silicon vias (TSVs) in 3-D integrated chips with consideration of the eddy currents in the surrounding Si substrate and coupling with horizontal interconnects. The model employs the vertical-to-vertical and horizontal-to-vertical 3D vector potential Green's function in layered media and is concise and sufficiently accurate in the entire range of interest for both the frequency and the center-to-center distance between TSVs. Along with the series impedances between horizontal wires, which are extracted from the discrete complex image method, as well as the TSV and horizontal wire capacitance values, the total loop impedance can be obtained. Our approach is verified against a full-wave finite- element-method electromagnetic solver High Frequency Structure Simulator, and it shows good accuracy (< 7% error) in the entire frequency range examined (up to 100 GHz). Given the fact that the formulated TSV series impedance model is purely analytical, the model could be efficiently used for system-level interconnect impedance extraction in emerging 3-D integrated systems. [ABSTRACT FROM AUTHOR]

A design methodology for distributing a buck converter filter for application to 3-D circuits is described. The 3-D filter exploits transmission line properties, permitting the generation and distribution of power supplies to different planes. As compared to a conventional LC filter, the proposed filter only requires on-chip capacitors without the use of on-chip inductors. Additionally, the physical structure of the filter simultaneously enables the distribution of the current to the load while filtering the switching signal at the input. A case study in a 0.18-\mum CMOS 3-D technology demonstrates the generation of a 1.2 V power supply delivering 700 mA peak current. [ABSTRACT FROM AUTHOR]

Based on the conformal mapping technique, a novel macro-\pi model is proposed to accurately predict the electrical performance of a low pitch-to-diameter ratio (P / D) through-silicon via (TSV) pair on the 3-D IC. The model combines the conventional resistance and inductance (RL) circuit with several parallel capacitances and conductance (CG) circuit. The accuracy-improved CG model rigorously considers the proximity effect. The model can be established by using the derived closed-form formula that is related to geometrical parameters of the TSVs. Compared with the conventional \pi-type model, the proposed model can significantly reduce the error of CG value from 25% to 2% with respect to a full-wave simulation, and thus the insertion loss can be well predicted from dc to 40 GHz. [ABSTRACT FROM PUBLISHER]

Below 360 ^\circ\C, we demonstrate germanium (Ge) \n^+/\p junction diode and n-channel Ge metal–oxide–semiconductor field-effect transistor (MOSFET) with a low-temperature \Al/Al2\O3/\GeO2 gate stack for monolithic 3-D integration using a metal-induced dopant activation (MIDA) technique. In particular, the cobalt (Co) MIDA phenomenon is investigated on Ge damaged by an implantation process. Shallow (\sim100 nm) source/drain junctions with very low resistivity (\5.2 \times \10^-4\ \Omega\-cm) are then achieved at very low temperature by the Co MIDA technique. Consequently, high diode and transistor current on/off ratios ( \sim\!\!\10^4 and \sim\!\!\10^3, respectively) are obtained in this n-channel Ge MOSFET. [ABSTRACT FROM PUBLISHER]

Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose a method to exploit the TSV C-V behavior in a p-silicon substrate to achieve minimum TSV capacitance during 3-D circuit operation. The nature of the TSV C-V characteristics depends both on TSV architecture and TSV manufacturing process, and both these factors should be optimized to obtain the minimum depletion capacitance in the desired operating voltage region. Measured C-V characteristics of the TSV demonstrate the effectiveness of the method. [ABSTRACT FROM AUTHOR]