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Nonvolatile magnetic RAM (MRAM) offers high cell density and low leakage power. This paper reports on using a 3-D integration technology based on through-silicon vias, to stack disparate memory technologies (e.g., SRAM and MRAM) together onto chip multiprocessors. In this paper, we explore the design of a 3-D stacked nonuniform hybrid SRAM/MRAM L2 cache architecture (NUCA) using the on-chip network to mitigate the interconnection problem. In addition, this paper investigates the problem of partitioning shared SRAM/MRAM hybrid L2 cache and placing cache data into the partitioned 3-D stacked hybrid NUCA for concurrently executing multiple applications in order to improve the system performance in terms of instructions per second while considering the heterogeneous characteristics in interconnection wire delay, memory cell density, memory access latency, and memory power consumption in a 3-D stacked hybrid SRAM/MRAM L2 cache. Experimental results show that the proposed runtime method with a 3-D stacked hybrid L2 cache improves performance by 61%, energy efficiency, i.e., energy-delay product by 53%, and storage lifetime by 15.6 times on average compared with the conventional SRAM-only L2 cache or MRAM-only L2 cache with the similar area. [ABSTRACT FROM PUBLISHER]

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and low-latency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to $\times 2.11$ and $\times 1.11$ improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu–Cu TSV bonding techniques, respectively. [ABSTRACT FROM AUTHOR]

Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e.g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems. In this paper, we propose a runtime thermal management method for CMPs with the 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling of processing cores in a temperature- and energy-aware manner. Experimental results show that the proposed runtime method with the 3-D stacked hybrid L2 cache offers up to 107.37% (55.28% on average) performance improvement and 88.47% (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-D stacked SRAM-based L2 cache. [ABSTRACT FROM AUTHOR]

3-D integration is a new technology that overcomes the limitations of 2-D integrated circuits, e.g., power and delay induced from long interconnect wires, by stacking multiple dies to increase logic integration density. However, chip-level power and peak temperature are the major performance limiters in 3-D multi-core architectures. In this paper, we propose a runtime power management method for both peak power and temperature-constrained 3-D multi-core systems in order to maximize the instruction throughput. The proposed method exploits dynamic temperature slack (defined as peak temperature constraint minus current temperature) and workload characteristics (e.g., instructions per cycle and memory-boundness) as well as thermal characteristics of 3-D stacking architectures. Compared with existing thermal-aware power management solutions for 3-D multi-core systems, our method yields up to 34.2% (average 18.5%) performance improvement in terms of instructions per second without significant additional energy consumption. [ABSTRACT FROM AUTHOR]