1. A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
- Author
-
Dartizio, Simone M., Tesolin, Francesco, Mercandelli, Mario, Santiccioli, Alessio, Shehata, Abanob, Karman, Saleh, Bertulessi, Luca, Buccoleri, Francesco, Avallone, Luca, Parisi, Angelo, Lacaita, Andrea L., Kennedy, Michael P., Samori, Carlo, and Levantino, Salvatore
- Subjects
PHASE detectors ,PHASE-locked loops ,COMPLEMENTARY metal oxide semiconductors ,NOISE - Abstract
This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm2 and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer- $N$ synthesized channels, 79.7 fs for typical fractional- $N$ channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of −51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of −252.8 dB and −251.6 dB for integer- $N$ and fractional- $N$ channels, respectively. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF