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This paper presents a novel dual mode configurable and tunable power amplifier (PA) that achieves a wide-bandwidth and high gain across a operational frequency spectrum of 20 to 30 GHz. The proposed PA used two-stage tunable PA which can be configured as a tunable synchronous mode or tunable stagger-tuned mode PA. PA is implemented by using a distortion-free varactor at the input and output tank of PA. The designed PA includes a high-Q CMOS active inductor (CAI) which provides a widely tunable output matching network. The resistive feedback is used for self-biasing in the designed PA which helps to enhance the linearity, stability of common source (CS) amplifier. The inter-stage impedance matching network consists of shunt and series resonance circuits are employed for maximum power added efficiency (PAE). Furthermore, the capacitive coupled reuse technique is implemented in each stage between the cascaded transistor to reduce the power consumption. A proposed PA is designed using a 65 nm CMOS technology. A measured power gain at the synchronous operation of PA is 28.4 ±0.5 dB with 1.31 GHz bandwidth while power gain at staggered operation is 22.1 ±0.5 dB with 3.71 GHz bandwidth. The measured saturated power (P sat) is 14.21 dBm and the noise figure (NF) is 5.2 dB. The group delay (GD) variation for staggered operation is 57 ±10 ps from 20-30 GHz. A proposed PA exhibits good linearity (IIP3) of 14.5 dBm and PAE is 47.5 % at 24 GHz. The power consumption of a designed PA is 48.56 mW with a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer's linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer's transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm 2 . [ABSTRACT FROM AUTHOR]