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Brain-inspired hyperdimensional (HD) computing models cognition by exploiting properties of high dimensional statistics—high-dimensional vectors, instead of working with numeric values used in contemporary processors. A fundamental weakness of existing HD computing algorithms is that they require to use floating point models in order to provide acceptable accuracy on realistic classification problems. However, working with floating point values significantly increases the HD computation cost. To address this issue, we proposed QuantHD, a novel framework for quantization of HD computing model during training. QuantHD enables HD computing to work with a low-cost quantized model (binary or ternary model) while providing a similar accuracy as the floating point model. We accordingly propose an FPGA implementation which accelerates HD computing in both training and inference phases. We evaluate QuantHD accuracy and efficiency on various real-world applications, and observe that QuantHD can achieve on average 17.2% accuracy improvement as compared to the existing binarized HD computing algorithms which provide a similar computation cost. In terms of efficiency, QuantHD FPGA implementation can achieve on average 42.3 × and 4.7 × (34.1 × and 4.1 × ) energy efficiency improvement and speedup during inference (training) as compared to the state-of-the-art HD computing algorithms. [ABSTRACT FROM AUTHOR]

Brain-inspired hyperdimensional (HD) computing emulates cognition by computing with long-size vectors. HD computing consists of two main modules: encoder and associative search. The encoder module maps inputs into high dimensional vectors, called hypervectors. The associative search finds the closest match between the trained model (set of hypervectors) and a query hypervector by calculating a similarity metric. To perform the reasoning task for practical classification problems, HD needs to store a non-binary model and uses costly similarity metrics as cosine. In this article we propose an FPGA-based acceleration of HD exploiting Computational Reuse ($\mathtt {HD}$ HD - $\mathtt {Core}$ Core ) which significantly improves the computation efficiency of both encoding and associative search modules. $\mathtt {HD}$ HD - $\mathtt {Core}$ Core enables computation reuse in both encoding and associative search modules. We observed that consecutive inputs have high similarity which can be used to reduce the complexity of the encoding step. The previously encoded hypervector is reused to eliminate the redundant operations in encoding the current input. $\mathtt {HD}$ HD - $\mathtt {Core}$ Core , additionally eliminates the majority of multiplication operations by clustering the class hypervector values, and sharing the values among all the class hypervectors. Our evaluations on several classification problems show that $\mathtt {HD}$ HD - $\mathtt {Core}$ Core can provide $4.4\times$ 4. 4 × energy efficiency improvement and $4.8\times$ 4. 8 × speedup over the optimized GPU implementation while ensuring the same quality of classification. $\mathtt {HD}$ HD - $\mathtt {Core}$ Core provides $2.4\times$ 2. 4 × more throughput than the state-of-the-art FPGA implementation; on average, 40 percent of this improvement comes directly from enabling computation reuse in the encoding module and the rest comes from the computation reuse in the associative search module. [ABSTRACT FROM AUTHOR]