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In recent years, there has been a breakthrough in integrated circuit technology, which has enabled the full integration of systems on a single chip and the development of increas ingly compact and low-power devices, such as IoT devices and smart devices. Usually, these devices come equipped with sensors and transceivers that make the interaction between the analog world and the digital world. In some of these devices Delta-Sigma modeling ( ∆Σ) is used to make the conversion from analogue to digital (ADC). In addition, the linear voltage regulator Low Dropout (LDO) is commonly used as the reference voltage buffer for the ADC ∆Σ. Since it is intended to do full system integra tion on a chip it is necessary to perform LDO integration. However, the LDO usually requires an external capacitor on the order of micro Farads to ensure stability, which makes integration of this circuit impossible. Currently, there are studies of LDO that do not need an external capacitor to be integrated into a chip. Among the proposals analyzed, it was found that some LDO are designed to have fast transient response and others, high PSRR. However, designing an LDO with these characteristics comes with new challenges such as ensuring stability, preventing PSRR degradation, and ensuring the speed of the transient response without causing an increase in the power consumed by the LDO. Traditionally, between the LDO and the ADC there is a switch switching very quickly, knowing the switching interval of the switch. Thus, in the present study a new architec ture is presented, based on the traditional LDO, but with a Miller compensation circuit that adapts to the load current. This compensation circuit allows to guarantee the sta bility and transient response of the circuit in each state of the current in the load. The developed LDO can achieve a gain of 77.3 dB, the PSRR at frequency of 1 kHz is 78.72 dB, when the IL = 20 .T hecurrentconsumedbytheLDOis IQ = 49.69 microA and when the switch between the LDO and the ADC is turned on, the IL transitions from 0 Ato20 milliA and takes 77.71 nanos until it stabilizes and provides a stable voltage to the ADC. Nos últimos anos, tem se verificado um avanço na tecnologia dos circuitos integrados, que tem permitido fazer a integração total de sistemas num único chip e o desenvolvimento de dispositivos cada vez mais compactos e de baixa potência, como os dispositivos IoT e smart devices. Normalmente estes dispositivos vêm equipados com sensores e transcetores que fazem a interação entre o mundo analógico e mundo digital. Em alguns destes dispositivos é utilizada a modelação Delta-Sigma ( ∆Σ) para fazer a conversão do analógico para o digital (ADC). Para além disso, é comummente usado o regulador de tensão linear Low Dropout (LDO) como buffer de tensão de referência para o ADC ∆Σ. Como se pretende fazer a integração total do sistema num chip é necessário realizar a integração do LDO. Contudo, o LDO normalmente necessita de um condensador externo na ordem dos micro Farads para assegurar a estabilidade, o que impossibilita a integração deste circuito. Atualmente, existem estudos de LDO que não precisa de ter um condensador externo para se realizar a integração deste, num chip. Entre as propostas analisadas verificou-se que alguns LDO são desenvolvidos por forma a ter rápida resposta transitória e outros, elevado PSRR. Contudo, projetar um LDO com essas características vem com novos desafios como assegurar a estabilidade, prevenir a degradação do PSRR, e garantir a velocidade da resposta transitória sem causar o aumento da potência consumida pelo LDO. Tradicionalmente, entre o LDO e o ADC há um interruptor a comutar muito rapidamente, conhecendo-se o intervalo de comutação do interruptor. Desta forma, no presente estudo é apresentada uma nova arquitetura, baseada no LDO tradicional, mas com um circuito de compensação de Miller que se adapta à corrente da carga. Este circuito de compensação permite garantir a estabilidade e a resposta transitória do circuito em cada estado da corrente na carga. O LDO desenvolvido consegue atingir um ganho de 77,3 dB, o PSRR a frequência de 1 kHz é 78,72 dB, quando o IL = 20 mA. A corrente consumida pelo LDO é IQ = 49,69 µA e quando o interruptor entre o LDO e o ADC é ligado, o IL transita de 0A para 20 mA e demora 77,71 ns até estabilizar e fornecer uma tensão estável ao ADC.

In analog to digital conversion, it’s necessary to provide a reference voltage to the Analog to Digital Converter (ADC), in order to quantify the input signal. However, as the ADC has a switch constantly commuting on its input it will cause perturbations on the reference voltage provided by the Bandgap circuit. Thus, it will interfere with the normal behaviour of the Bandgap circuit, which will longer be capable of provide the desired reference voltage. Besides, if the reference voltage is not constant in the desired value the output code generated by the ADC will have errors. In order to avoid conversion errors it will be needed to introduce a buffer between the Bandgap and the ADC. Thus, taking advantage from the characteristics of the buffer (low output impedance, high input impedance and unitary gain) the system will be capable of recover from the perturbations introduced by the ADC in the reference voltage. Therefore, in this thesis are studied some of the already existing architectures of buffers, in order to see the advantages and disadvantages of each one. This way were chosen the best three architectures from a theoretical point of view, to implement and simulate, to obtain all the needed information in order to better compare them.

Nowadays, electronic devices are ubiquitous. This spread across all scientific fields has allowed for greater development of solutions for problems once thought impossible, or impractical, to solve. Most specifically, it leads to a constant cost reduction in previously expensive technology, to a point where university students can acquire these devices and tinker with them, even finding applications that were not initially thought for the device. As a result, we began the development of this e-nose system, since it became increasingly important to know and understand the constituents and source of a chemical sample. This dissertation arises from the need to integrate the computational power inherent to a low-cost microcontroller unit, to identify chemical substances and their characteristics. With the main goal set, it was possible to formulate the guidelines to achieve a successful data acquisition channel for an e-nose system implementation with reduced costs, size and fast execution. The starting point consisted in understanding how previous implementations of this system work, as well as its most basic components. After researching and studying e-nose technologies, I was able to define two separate segments for a data acquisition channel: acquisition & communication module (hardware) and a data pre-processing module (software). By using a conductive polymer sensor with a PSoC 5LP microcontroller unit, it was possible to detect changes in the sensor response according to the chemical sample being tested, acquire this signal with the Delta Sigma ADC and, straight away, send this data to the computer where it would be pre-processed. This stage was implemented in Python and with its extensive signal processing libraries. Its main goal was to receive and store the data so that it could be use on a future pattern recognition algorithm to reach the final e-nose conclusion. Since this displayed to the user, a GUI was developed, and the resulting acquisitions could be displayed in several plots, as a way of verifying a successful operation. In the end, it was a success, since after performing acquisition, communication and displaying the results, subtle differences were visible on the plots displayed.