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Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by 1. 1 × while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time. • Anti-Series Diode arrangement based ring amplifier is proposed to improve the dead zone voltage and the settling time. • RC electrical equivalent model for the settling time analysis of the circuit. • Proposed ring amplifier circuit is robust against the PVT variations. [ABSTRACT FROM AUTHOR]

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude. [ABSTRACT FROM AUTHOR]

This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The “scope-on-chip” captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation. [ABSTRACT FROM AUTHOR]

This article presents a 14-b 100-MS/s single-channel pipelined-successive-approximation register (SAR) ADC using a weighted-averaging correlated level shifting (WACLS) technique. For a closed-loop residue amplification, the error voltage due to the finite operational amplifier (opamp) gain can be ideally removed by the proposed WACLS technique with a low-gain opamp. In addition, the opamp bandwidth degradation, by an extra level-shift capacitor ($C_{\mathrm {LS}}$) in two-phase amplification CLS-based circuits, can be relaxed and minimized in WACLS. Furthermore, a speed-enhancement scheme is provided to alleviate the speed degradation owing to one extra amplification phase and long bit-cycling time from two-phase amplification and SAR circuits, respectively. A modified reference swapping (RS) technique is applied to diminish the capacitor mismatch error without any calibration. A quick startup ring amplifier design is introduced for duty-cycled control power saving. The chip is implemented in the 28-nm CMOS technology and occupies an active area of 0.018 mm2. At 100 MS/s and Nyquist-rate input, the measured SNDR is 71.7 dB with 0.7-mW power consumption only. The calibration-free ADC achieves Walden and Schreier figure-of-merit of 2.2 fJ/conversion-step and 180.2 dB, respectively. Compared with the prior-art ADCs with sampling frequency > 100 MS/s and SNDR > 65 dB, this work advances the state-of-the-art by 3 $\times $ and 5.3 dB, respectively. [ABSTRACT FROM AUTHOR]

This brief presents a novel adaptive slew-rate ring amplifier. The proposed technique enhances the linearity, without stability degradation, using a rail-to-rail controlled feed-forward path used in parallel with the main ring amplifier. It offers additional degrees of freedom to improve the linearity/power consumption trade-off proposed in other reported slew-rate enhancement techniques. The proposed design has been implemented and simulated in a low-cost CMOS 65 nm technology. Operating from a single 0.9 V power supply, it consumes $186~\mu \text{A}$ for switching frequency of 210MHz. For the same current consumption, it achieves an improvement of 10 dB in the total harmonic distortion (THD) compared to state-of-the-art. [ABSTRACT FROM AUTHOR]

The ring amplifier is an energy efficient and high output swing alternative to an OTA for switched-capacitor circuits. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. This paper presents a self-biased ring amplifier scheme that makes the ring amplifier more practical and power efficient while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. We introduce an improved auto-zero scheme that eliminates the gain error caused by the parasitic capacitance across the auto-zero switch. Furthermore, a comparator-less pipeline ADC structure takes advantage of the characteristics of the ring-amplifier to replace the sub-ADC in each pipeline stage. The prototype ADC has measured SNDR, SNR and SFDR of 56.6 dB (9.11 b), 57.5 dB and 64.7 dB, respectively, for a Nyquist frequency input sampled at 100 MS/s, and consumes 2.46 mW. [ABSTRACT FROM PUBLISHER]

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18\, \mum CMOS technology and achieves 76.8~dB SNDR and 95.4~dB SFDR at 20 Msps while consuming 5.1~mW, achieving a FoM of 45 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]