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Among all basic arithmetic operations, the division is the most complex one. On the other hand, working on post‐complementary metal–oxide–semiconductor (CMOS) technology attracts attention of many researchers, while the progress of miniaturisation in CMOS technology faced physical limits. Therefore, in this study, the authors propose a non‐restoring divider in quantum‐dot cellular automata (QCA), as one of the most promising technology. To achieve an efficient divider, they propose a novel 1 bit full‐adder and take advantage of improved design of XOR gate. This design has considerable improvements in terms of cell numbers, delay and area, compared with other dividers. The suggested design is simulated in QCADesigner software and acceptable results are achieved. [ABSTRACT FROM AUTHOR]

Decimal X\times Y multiplication is a complex operation, where intermediate partial products (IPPs) are commonly selected from a set of precomputed radix- 10~X multiples. Some works require only [ 0, 5 ]\times X via recoding digits of Y to one-hot representation of signed digits in $ [-5, 5]$ . This reduces the selection logic at the cost of one extra IPP. Two’s complement signed-digit (TCSD) encoding is often used to represent IPPs, where dynamic negation (via one xor per bit of $X$ multiples) is required for the recoded digits of $Y$ in $[-5, -1]$ . In this paper, despite generation of 17 IPPs, for 16-digit operands, we manage to start the partial product reduction (PPR) with 16 IPPs that enhance the VLSI regularity. Moreover, we save 75% of negating xors via representing precomputed multiples by sign-magnitude signed-digit (SMSD) encoding. For the first-level PPR, we devise an efficient adder, with two SMSD input numbers, whose sum is represented with TCSD encoding. Thereafter, multilevel TCSD 2:1 reduction leads to two TCSD accumulated partial products, which collectively undergo a special early initiated conversion scheme to get at the final binary-coded decimal product. As such, a VLSI implementation of $16\times 16$ -digit parallel decimal multiplier is synthesized, where evaluations show some performance improvement over previous relevant designs. [ABSTRACT FROM AUTHOR]

Han propose a new method for parallel decimal multiplication with redundant partial products. They compare the performance of their multiplier with some previous relevant works, based on analytical and synthesis results. We have noted that the claimed critical delay path in (IEEE Trans. Computers, vol. 62, no. 5, pp. 956–968, May 2013) is faster than the actual critical delay path. Therefore, comparison results seem to be deceptive. For example, our accurate analytical evaluation devaluated the claimed speed advantage over the multiplier of (Microelectronics J., vol. 40, no. 10, pp. 1471–1481, Oct. 2009). Furthermore, we synthesized both multipliers, to show synthesis results confirm those of analytical evaluation. [ABSTRACT FROM AUTHOR]