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The post‐silicon validation and debug is the most important task in the contemporary integrated circuit design methodology. The vital problem prevailing in this system is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize state reconstruction. In the reported works, to select and to restore the signals efficiently it is categorized into two types like low simulation with high‐quality technique and high simulation with low‐quality technique. In this work, a node‐based combinational gate signal selection algorithm is proposed based on machine learning method that maximizes the state restoration capability. A significant improvement (80%) has made to achieve adequate simulation time with the high‐quality associated with the state‐of‐the‐art of supplementary methods. [ABSTRACT FROM AUTHOR]

Hypergraphs are tools for matching of point-features incorporating spatial relationships in the form of hyperedges exhibiting topological and geometric features between the points of images to be matched. Considering all possible hyperedges is computationally expensive and are randomly chosen in the state of the art techniques. A Helly Hypergraph based Matching Framework (HHMF) is proposed for the matching of images using point-features with effective hyperedges. The framework includes proposed algorithms such as Construction of Hyperedges using Point-features by Random (CHPR), Combinatorial (CHPC), and Exhaustive (CHPE) sampling techniques with and without Helly selection. The resultant hyperedges are treated with Adaptive Block Co-ordinate Ascent Graph Matching with Integer Projected Fixed Point algorithm. The performance of the proposed framework is evaluated in terms of Accuracy, Matching score, Execution time and Tensor Size for synthetic point sets and Willow wine image dataset. Based on the experimental studies carried out against existing framework, CHPC, and CHPE with Helly selection, exhibited better performance with 73.88% & 81% accuracy for 53.64 & 14.8% reduced tensor size respectively, in deformation noise tests, and 98% & 96% accuracy for 97% & 70% reduced tensor size in outlier tests. In the implicit experimental comparisons within sampling techniques, CHPR, and CHPE provided better performance with 81.37%, and 76% accuracy. In general, HHMF framework has reduced the tensor size and execution time for deterministic sampling cases during point sets matching. The framework can be extended in the near future by incorporating learning schemes for automated hypergraph based point sets matching. [ABSTRACT FROM AUTHOR]

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies. [ABSTRACT FROM AUTHOR]